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Combining test and measurement expertise with data science and big data engineering, the PathWave Manufacturing Analytics platform provides actionable insights for every level in your organization in the smart factory of the future. Improve yield, lower retest and handling, and lower the cost of poor quality with big data advanced analytics that really works. Accelerate your Return on Investment and business outcomes with unique, innovative analytics.

Descriptive

• View your factory performance in terms of Overall Operating Efficiency (OEE), yield, first pass yield, retest, volume, etc. with extensive drilldowns and filters
• Save the workspace and see your own personalized dashboard on demand, real-time from anywhere

Diagnostic

• Use no-code specially curated diagnostic tools and visualizations for all levels of operators, technicians and engineers
• Root cause issues with just a few clicks, compare between multiple tests, systems, fixtures, parts, probes and more

 Predictive

• Predict potential quality issues in real-time manufacturing with optimized machine learning anomaly detection models
• Get only “high severity scored” alerts. Take action to prevent catastrophe and mitigate the risks of poor quality without alert fatigue

Prescriptive

• Prescribe real-time adaptive test limits with optimized dynamic part averaging testing
• Leverage transformed data and insights for horizontal and vertical systems to optimize processes

• Intelligent architecture - supports C/C++, VB, C#, VB.NET, Keysight VEE, and more
• Switch Manager - streamlines the task of switching topology configuration
• Test Profiler - evaluates and optimizes the performance throughput of individual tests
• Throughput Multiplier - increases throughput through batch testing for multiple UUTs
• Reusable library - provides framework for code reuse (handlers, actions, and test sequences)
• Multithreading – executes multiple test statements simultaneously
• Operating system Test Exec SL 8.1: Window® 10. Windows® 7 Professional or Home Edition, Service Pack 1 or later
• Operating system Test Exec SL 7.1: Windows® 7 32-bit or 64-bit Professional or Home Edition, Service Pack 1 or later. Windows® XP Professional or Home Edition, Service Pack 2 or later. Windows® 2000 Professional, Service Pack 4 or later

Keysight Technologies' TestExec SL is a customizable, flexible test executive developed specifically for electronics manufacturing functional test applications. This off-the-shelf test executive empowers test developers with a fully customizable operator interface, open architecture for multiple instrument integration, flexible test sequencing, easy debugging tools, and provisions for line integration in most manufacturing test environments. TestExec SL boosts productivity, offers unique advantages for test automation, and is unbeaten for ease of use. With the new release of TestExec SL 7.1, you can utilize the multithreading feature to improve execution throughput and reduce idle time.

User manual and help file for TestExec SL are available in the installation files.

Automate Testing with TestExec SL

• Intelligent architecture - supports C/C++, VB, C#, VB.NET, Keysight VEE, and more
• Switch Manager - streamlines the task of switching topology configuration
• Test Profiler - evaluates and optimizes the performance throughput of individual tests
• Throughput Multiplier - increases throughput through batch testing for multiple UUTs
• Reusable library - provides framework for code reuse (handlers, actions, and test sequences)
• Multithreading – executes multiple test statements simultaneously
• Asynchronous testing capabilities to better optimize test time and utilization

Keysight Technologies' TestExec SL is a customizable, flexible test executive developed specifically for electronics manufacturing functional test applications. This off-the-shelf test executive empowers test developers with a fully customizable operator interface, open architecture for multiple instrument integration, flexible test sequencing, easy debugging tools, and provisions for line integration in most manufacturing test environments. TestExec SL boosts productivity, offers unique advantages for test automation, and is unbeaten for ease of use.

Boundary scan is a method for testing interconnections on printed circuit boards. Keysight’s Interconnect Plus Boundary Scan feature enables all the tools required to develop and execute this foundational test method on the board under test.

When a number of boundary scan compliant devices are chained together, the Interconnect Plus boundary scan test checks that all the interconnecting pins on the devices within the chain are making electrical contact with the printed circuit board.

When the Interconnect Plus Boundary Scan feature is enabled, the powered shorts, interconnect, bus wire, connect, and chain disable tests are automatically generated according to the IEEE 1149.1 standards with the test patterns defined for the most efficient and complete test coverage for the devices under test.

Boundary scan is a method for testing interconnections on printed circuit boards. Keysight’s Interconnect Plus Boundary Scan feature enables all the tools required to develop and execute this foundational test method on the board under test.

When a number of boundary scan compliant devices are chained together, the Interconnect Plus boundary scan test checks that all the interconnecting pins on the devices within the chain are making electrical contact with the printed circuit board.

When the Interconnect Plus Boundary Scan feature is enabled, the powered shorts, interconnect, buswire, connect, and chain disable tests are automatically generated according to the IEEE 1149.1 standards with the test patterns defined for the most efficient and complete test coverage for the devices under test.

Boundary scan is a method for testing interconnections on printed circuit boards. Keysight’s Interconnect Plus Boundary Scan 1149.6 feature enables all the tools required to develop and execute this test method on the board under test. Compared to the 1149.1 standards, the 1149.6 standards define test methods for boundary scan devices that are designed with AC coupled signals or differential nets needed for high-speed operations of the device.

When enabled, the Interconnect Plus Boundary Scan 1149.6 development tools will automatically generate the 1149.6 tests when 1149.6 compliant devices are detected on the printed circuit board.

Keysight has the most comprehensive test patterns for 1149.6 testing. Defects such as shorts or opens on the differential pins and missing coupling capacitors can be detected.

Boundary scan is a method for testing interconnections on printed circuit boards. Keysight’s Interconnect Plus Boundary Scan 1149.6 feature enables all the tools required to develop and execute this test method on the board under test. Compared to the 1149.1 standards, the 1149.6 standards define test methods for boundary scan devices that are designed with AC coupled signals or differential nets needed for high-speed operations of the device.

When enabled, the Interconnect Plus Boundary Scan 1149.6 development tools will automatically generate the 1149.6 tests when 1149.6 compliant devices are detected on the printed circuit board.

Keysight has the most comprehensive test patterns for 1149.6 testing. Defects such as shorts or opens on the differential pins and missing coupling capacitors can be detected.

Boundary scan is a method for testing interconnections on printed circuit boards. Keysight’s Silicon Nails feature enables all the tools required to develop and execute tests on non-compliant boundary scan devices that are connected to boundary scan compliant devices on the printed circuit board.

During test development, the Silicon Nails test development tool references the digital test defined for the non-compliant boundary scan device. Then, it will generate a boundary scan test that drives the boundary scan devices on the chain to execute the test vectors on the non-compliant boundary scan device. So, the tester is driving the non-compliant boundary scan device and testing it through the boundary scan chain.

The Silicon Nails test development tool also allows users to define the vectors that they would like to execute on the non-compliant boundary scan device. The test development tool will generate the boundary scan test to output or input at the relevant interconnecting pin, thus generating the test consistently.

Boundary scan is a method for testing interconnections on printed circuit boards. Keysight’s Silicon Nails feature enables all the tools required to develop and execute tests on non-compliant boundary scan devices that are connected to boundary scan compliant devices on the printed circuit board.

During test development, the Silicon Nails test development tool references the digital test defined for the non-compliant boundary scan device. Then, it will generate a boundary scan test that drives the boundary scan devices on the chain to execute the test vectors on the non-compliant boundary scan device. So, the tester is driving the non-compliant boundary scan device and testing it through the boundary scan chain.

The Silicon Nails test development tool also allows users to define the vectors that they would like to execute on the non-compliant boundary scan device. The test development tool will generate the boundary scan test to output or input at the relevant interconnecting pin, thus generating the test consistently.

The i3070 In-Circuit Test System architecture is split into 4 modules. Each module can execute tests in parallel with the rest, so you can test 4 printed circuit boards at one time.

For cases when you need to test homogeneous (identical) boards with more than 1000 nodes each, you can combine 2 modules together using the Advanced Throughput Multiplier feature. This allows you to test up to two 1000 to 2000 node (between 1296 and 2592 nodes) boards simultaneously on a 4 module tester, thus dividing the test time by half.