XE8-class M8050A 120 Gbaud High-Performance Bit Error Ratio Tester (BERT)

The Keysight M8050A BERT supports the development and deployment of high-speed SerDes chips and devices for 800G/1.6T Ethernet, OIF-CEI-112G/224G, PCIe, USB 3.2/4, and other technologies. It combines 120 GBd signaling with high signal integrity.  Transmitter (Tx), channel, and receiver (Rx) form the physical layer (PHY) of a serial high-speed communication system: the receiver detects, retimes, and “cleans up” the received signal. Receiver tests determine its ability to recover an impaired signal and maintain a required bit error ratio (BER). BER is the ratio of the number of incorrectly received bits to the total number of bits transmitted over a communication channel.  The Keysight M8050A high-performance bit error ratio tester (BERT) platform enables accurate characterization of high-speed digital receivers used in next-generation data center networks and server interfaces with symbol rates up to 120 GBd. The M8050A high-performance BERT is part of the Keysight M8000 Series of BER test solutions. It can be combined with other hardware and software of the M8000 Series including modules from the M8040A platform such as the M8045A, M8046A, and M8054A modules.  The M8050A combines pattern generation, clocking with integrated jitter, channel emulation, and error analysis in one modular AXIe platform. Values are typical or nominal; warranted specifications are given in the Data Sheet.  The M8042A pattern generator module supports symbol rates from 2 to 120 GBd and is available in one-channel or two-channel configurations. Three symbol-rate ranges can be selected: up to 32 GBd, up to 64 GBd, and up to 120 GBd. The M8042A requires an M8009A clock module with jitter modulation capabilities and one remote head per data output channel.  The M8042A high‑performance pattern generator module provides built‑in transmitter de‑emphasis, enabling realistic signal conditioning directly at the pattern generator output. This capability allows users to compensate for channel loss and emulate transmitter behavior specified in high‑speed serial standards without requiring external signal conditioning components. The M8042A provides built-in de-emphasis with positive and negative cursors based on a Finite Impulse Response (FIR) filter.  The Automatic De‑emphasis Optimization feature (also referred to as “Auto De‑emphasis”) optimizes the de‑emphasis settings at the pattern generator output (remote head) to achieve optimal eye performance for NRZ or PAM4 signals. In addition, the feature supports cable and fixture de‑embedding or embedding using imported S‑parameter files. This feature is available for the M8042A pattern generator module with the M8058A, M8059A, M8068A, or M8069A remote head.  PCIe Tx equalization (TxEQ) de‑emphasis presets are standardized transmitter‑side settings that define predefined combinations of pre‑cursor, main cursor, and post‑cursor tap weights to compensate for frequency‑dependent channel loss. Introduced in Gen3 and used through Gen6 and beyond, these presets provide coarse transmit equalization options spanning short, low‑loss links to long, highly lossy channels, enabling interoperable and fast link training without full continuous tuning. During link equalization, the transmitter advertises its supported presets, and the receiver evaluates their signal quality.  The Keysight M8042A pattern generator module supports native Forward Error Correction (FEC) encoding and precoding in accordance with the IEEE 802.3cd and IEEE 802.3dj specifications, enabling realistic, PHY-compliant stimulus generation for advanced Ethernet interfaces. It implements the Reed-Solomon RS(544,514) “KP4” FEC at the PCS layer, including standards-compliant codeword framing, parity generation, scrambling, and distribution to PCS lanes. For KP4-based interfaces, precoding is supported to mitigate error propagation and improve post-FEC BER performance.