Intel Foundry Enables Pre-Silicon Validation for Next-Generation Chiplet Designs
Case Studies
Keysight EDA and Intel Foundry collaborated to support Embedded Multi-die Interconnect Bridge-T (EMIB-T) technology using Keysight Chiplet PHY Designer. The workflow supports emerging interconnect standards, including Universal Chiplet Interconnect Express 2.0 and Open Compute Project Bunch of Wires, to improve chiplet design flexibility and enable pre-silicon validation.
Open standards such as Universal Chiplet Interconnect Express (UCIe) and Bunch of Wires (BoW) are helping the industry create more consistent approaches to chiplet interconnect. However, adopting standards is only part of the challenge. Designers also need validation workflows that can confirm compliance and evaluate link margin before silicon is manufactured.
For Intel Foundry’s EMIB-T technology, the need is clear: advanced packaging must be supported by practical EDA workflows that help engineers evaluate performance earlier in the design process. Without pre-silicon validation, teams risk discovering issues too late, when changes can be costly and schedules are harder to protect.
Keysight EDA collaborated with Intel Foundry to support EMIB-T technology within Keysight Chiplet PHY Designer. EMIB-T is aimed at improving high-performance packaging solutions for AI and data center markets, including support for Intel 18A process node workflows.
The workflow supports a standards-based approach to chiplet design. By enabling engineers to evaluate compliance and link margin earlier, the solution helps address a major risk area in advanced semiconductor development: the gap between package-level design intent and real-world link behavior.