Characterization of DDR4 Receiver Sensitivity Impact on Post-equalization Eye
白皮書
White Paper from DesignCon 2017
This white paper was first published at DesignCon in January, 2017. Reprinted with permission from DesignCon.
Abstract
The current DDR4 specification for the receiver (Rx) sensitivity defined at the Rx input does not account for equalization functionalities implemented in advanced Rx designs and may lead to over-design. In this paper we present a novel approach to characterize the Rx sensitivity impact on Rx post-equalization signal. We demonstrate that at the Rx output timing impairment is induced by common mode variation. The resulting jitter can be represented by a deterministic jitter model and incorporated in the statistical eye calculation. Timing margin and jitter in the post-equalization eye is measured at Vref to eliminate over-design.