DDR3 Memory Protocol Analysis and Compliance Verification

DDR3 Memory Protocol Analysis and Compliance Verification

Keysight Technologies and FuturePlus Systems

Achieve straightforward and reliable DDR3 DIMM bus analysis at 2400MT/s and DDR3 SO-DIMM analysis at 1867MT/s

The Double Data Rate 3 (DDR3) memory specifications have increased the clock frequencies and data transfer rates for Dual Inline Memory Modules (DIMMs). These developments present new challenges in the design and debug of computer motherboards and DIMMs or SO-DIMMs (Small Outline DIMMs) incorporating the faster DDR3 technology, especially in the area of protocol analysis and verification.

The FuturePlus FS2361 DDR3 DIMM, FS2354 DDR3 64 bit SO-DIMM, and FS2355 DDR3 72 bit SO-DIMM interposers provide a mechanical, electrical and software interface between the Keysight Technologies U4154B logic analyzer and the DDR3 connector. The FS2361, FS2354, and FS2355 are used to design and debug computer motherboards and DIMMS or SO-DIMMs incorporating faster DDR3 technology.

The FS2361, FS2354, and FS2355 protocol decode software translates acquired signals into easily understood bus transactions, at the full bus speed. The Keysight logic analyzer provides extensive triggering and store qualification features. The FS2361 DIMM interposer can be configured to perform state analysis of Reads or Writes, or both Reads and Writes, at up to 2400 MT/s. The FS2354 and FS2355 SO-DIMM interposers can be configured to perform state analysis of Reads or Writes, or both Reads and Writes, at up to 1867 MT/s.

–Quick, easy connection between DDR3 DIMM or SO-DIMM connectors & Keysight U4154B logic analyzers

–Complete, accurate 2400MT/s state and timing analysis up to 12.5 GHz

–All signals are probed passively, does not require U4201A cables (except FS2354).

–Supports registered, unbuffered, and register DIMMs

–Burst sizes of 4, or 8 supported.

–Monitors writes only, reads only, or writes and reads simultaneously.

–Quick and easy setup using Keysight EyeScan with 5 ps/5 mV resolution

DDR3 Memory Protocol Analysis and Compliance Verification

The DDR3 protocol decode software executes in the logic analyzer. The user selects attributes such as Burst length, CAS, and Chip Selects to decode the key DDR bus signals. The logic analyzer displays the transaction type, address, data and command conditions and user-defined symbols. User-selectable post-processing filters allow the acquired data for different types of transactions to be displayed in different colors.

As timing and voltage margins continue to shrink, confidence in signal integrity becomes an increasingly vital requirement of the design verification process. Keysight’s EyeScan lets you quickly acquire comprehensive signal integrity information on the DDR3 bus in your design, and can provide measurements with 5 ps of resolution.

The FS2361 and FS2355 plug directly onto the Keysight logic analyzer U4154B module, maximizing the quality of the connection to the system under test. The FuturePlus DDR3 interposers, when used with an Keysight Technologies logic analyzer, allow you to achieve straight forward and reliable protocol analysis of your DIMM and SO-DIMM designs.