Optimizing High-Speed Connector Models for Channel Design at 56 Gbps and Above
白皮書
High-speed digital connectors used in Hyperscale Networks require both modeling and measurement correlation to meet the demanding bandwidth requirements of today’s internet infrastructure. It is now critical to have high signal integrity throughout the whole channel from mezzanine systems to backplane interconnects to SERDES (serializer-deserializer) chipsets. Emerging applications using 56Gbps and above are requiring new methods of validation, compared to the traditional metrics of BER and eye diagrams, to avoid throwing channel margin away unnecessarily. The Channel Operating Margin (COM) figure-of-merit along with measurement/simulation correlation is becoming a critical part of the design cycle. The analysis of the test cases proposed herein will present an extensive validation of a high-speed connector for differential interconnects working up to 112 Gbps, by providing an in-depth analysis of such component, as a critical portion of the channel. A comprehensive correlation of the connector model to experimental results in terms of thru and crosstalk responses in both time and frequency domains provides a reliable connector model for the subsequent channel design. Comparison of new test methodologies will be shown to accurately predict how to optimize channel performance at today’s ultra-fast data rates.