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Ensure PCIe design success and the integrity of your measurements with
the most complete PCI Express® 6.0 solution showing true design performance.
Keysight helps you improve time to market and streamlines your path to PCIe success with scalable solutions from simulation to protocol.
PCIe Design and Simulation
The design of high-speed serial data links becomes significantly more complex as data rates increase — channel topologies become more diverse, and the number of parameters that need to be tuned for active components multiply. You need to use simulation to optimize the signal and power integrity of your PCIe designs and analyze the electromagnetic (EM) effects of components such as high-speed integrated circuit (IC) packages and printed circuit board (PCB) interconnects. We can help you quickly and effectively evaluate the end-to-end performance of your PCIe 6.0 links.
PCIe Transmitter Test
PCI Express 6.0 is a revolutionary step with challenges never seen before, a move from NRZ to PAM4 with an eye height of only 6mV vs. 15 mV in PCI Express 5.0. To accurately measure eye heights as small as 6 mV you need the world’s best scope noise performance found in Keysight’s UXR scopes.
Keysight FlexPLL provides the fastest transmitter phase-locked loop (PLL) bandwidth measurement, reducing your measurement time from hours to seconds.
Our leading-edge transmitter test automation tools, developed by Keysight experts, ensure the integrity of your PCIe measurements, avoid costly redesigns and improve your time to market.
Infiniium UXR-Series Real-Time Oscilloscopes
D9050PCIC PCI Express 5.0 Transmitter Electrical Performance Validation and Compliance Software
N1081PLCA PCI Express PLL Test Application
D9040PCIC PCI Express Electrical Performance Validation and Compliance Software
PCIe Receiver Test
Extracting digital content from the PCIe signal is significantly more challenging with the PAM4 format and PCIe speeds reaching up to 64 GT/s.
At these high data transfer rates with PAM4 signals, PCIe receivers often receive a heavily degraded signal due to the channel’s high-frequency loss characteristics, resulting in unacceptable bit error ratios (BERs). Bit errors are handled with forward error correction (FEC); new measurements are required like signal-to-noise and distortion ratio (SNDR).
Keysight‘s M8040A high-performance BERT is the only PAM4-capable BERT approved for Gold Suite PCIe receiver test. We show you the true performance of your design to guarantee your PCIe success.
With Keysight by your side, you get a smooth transition from PCI Express 5.0 to 6.0.
PCIe Interconnects Test
The channel is one of the key elements of the PCIe system. There are many sources of distortion in the channel that can degrade signal quality from a PCIe transmitter to the PCIe receiver — crosstalk, jitter, and intersymbol interference (ISI) are a few examples. You must measure the loss characteristics across the channel to ensure they are within the limits defined by the PCIe specification for a given data rate. Scattering parameters (S-parameters) are used to characterize high-frequency circuits such as the channel in a PCIe system.
Keysight is a major contributor to the PCI-SIG primary working groups and has been since their inception. Keysight helps you navigate through these complex requirements with unmatched expertise and world-leading support.
PCIe Protocol Test
Protocol validation occurs at the physical layer, data link layer, and transaction layer. In addition to the mandatory protocol compliance tests, the PCI-SIG recommends more than a hundred additional tests to properly characterize your design. A key area of protocol test is link training and status state machine (LTSSM).
Once the physical layer of a PCIe link has allowed the link to train, you need to determine if data packets are reliably transferred between link partners. You need protocol analysis and exerciser tools to determine if your PCIe device can successfully communicate to its link partner. We can help you perform complex protocol tests and quickly debug any detected errors to ensure compliance with your PCIe devices.
5th Generation High-Speed Digital Designs Considerations
Simulating PCIe 5.0 Embedded System Design
White Papers 2022.08.12
PCI Express ® Test Overview
White Papers 2022.11.10
The Fast Track to PCIe® 5.0
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