Debugging the Real Performance of Your Design

The foundation of the P5551A is the improved signal integrity provided through the integrated design of the Exerciser card which provides a solid, trustworthy test platform. This compact design allowed Keysight engineers great versatility in ensuring that the P5551A would have signal integrity characteristics that could be configurable enough to be tuned for many different test environments, while also offering quick link up capability for test cases that focus on higher layer protocol debugging.  The P5551A is designed to be easy to setup, connect, and be quickly configured to bring up the PCIe link and check basic LTSSM and protocol functionality. To support this the P5551A has many features included that allow for quick validation of fundamental PCIe features.

  • Supports up to 32GT/s with x4, x8, and x16 physical lane width options
  • Automated Link training with skip and bypass support 
  • Traffic generation with lane reversal and polarity detection 
  • Scalable flow control support 
  • Link training and LTSSM control
  • Real-time equalization
  • Transactional Layer Generation
  • Error insertion
  • Complete RAS test protocol solution

Key Specifications

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P5551A PCIe 5.0 Protocol Exerciser

P5551A PCIe 5.0 Protocol exerciser supports

  • 2.5GT/s (Gen1) through 32 GT/s (Gen5)
  • CEM connection with x4, x8 and x16 physical lane width support
  • LTSSM tester
  • Link and lane configuration
  • Replay function
  • Equalization and transceiver configuration
  • Skip configuration
  • Customized traffic generation
  • Power management
  • Automation API
P5551A PCIe 5.0 Protocol Exerciser

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