End-to-End System-Level Simulations with Repeaters for PCIe® Gen4
白書
The design solution space for high-speed serial links is becoming increasingly complex as data rates increase, channel topologies become more diverse, and tuning parameters for active components multiply. PCI-Express (PCIe) Gen-4 is a particularly relevant example of an application whose design solution space can be a daunting problem to tackle, especially when each link can contain three active components: Root Complex (RC), Repeater, and End Point (EP). This paper presents a how-to guide for defining, executing, and analyzing system-level simulations involving all three components.
The use of a Repeater to extend the reach between RC and EP over extremely lossy channels is a common practice and can present unique challenges in examining the design solution space. The Repeater’s settings must be co-optimized together with SerDes transmitter (Tx) and receiver (Rx) settings to maximize the overall link performance.