Data Sheets
Keysight Technologies
Advanced Design System (ADS)
W2360EP/ET SIPro Signal Integrity EM Analysis
W2359EP/ET PIPro Power Integrity EM Analysis
New Cohesive Workflow Redefines SI/PI Solutions
Signal Integrity (SI) and Power Integrity (PI) are often treated as separate design tasks that are closely interrelated, with the same end-goal for a design: Ensure high-speed link performance and system-level reliability.
Consider now a single user interface for both PI and SI analyses, where one setup can be easily copied from one analysis-type to another, with simulations run in the same environment. In ADS, SIPro and PIPro deliver this ideal, sharing a common GUI, workflow, model database, and results visualization; eliminating the need to switch between different point tools, and allowing better collaboration between engineers. Furthermore, with the high-capacity EM solvers in SIPro and PIPro, it is no longer necessary to spend hours manually simplifying designs, reducing size by cookie-cutting and removing layers and nets, that is typically required with general purpose EM tools.
SIPro
A Fraction of the Full Wave 3DEM Simulation Time
SIPro provides signal integrity analysis of your high-speed PCBs. It empowers you to characterize loss and coupling of signal nets, signal and power nets, and complete ground nets at once. The resulting EM model can be transferred to the ADS Transient and Channel Simulators in one seamless flow.
Speed and accuracy
Layout to results in less than 20 clicks
Innovations in EM - Mesh Domain Optimization
SIPro
The following analyses can be performed in SIPro:
EM model extraction
Complete channel analysis
PIPro
Accurate and Efficient Net-Driven PI Analysis
PIPro provides power integrity analysis of your power distribution network (PDN), including DC IR drop analysis, DC IR Drop Electro-Thermal analysis, AC impedance analysis and power plane resonance analysis.
Speed and accuracy
Designed for usability
DC IR drop analysis
Power plane resonance analysis
Results reporting
DC IR Drop Electro-Thermal
As power delivery networks are forced into tighter PCB real-estate, the power plane becomes far from idealized. The power and ground planes become heavily perforated with clearance holes from signal vias and stitching vias. It can be a struggle for the layout engineer to get the required current up into the package of the device that requires it, without passing through narrow traces of metal. Calculating an accurate IR-Drop is important for the PI designer, but also knowing the absolute temperature that the PDN traces, vias and chip die will reach, is invaluable information. High temperatures can cause reliability issues; as the temperature cycles from on/off states can cause the via barrels to weaken and crack over time.
It is not intuitive to the designer whether a via is undersized for the current that is passing through it. The temperature rise is very dependent on the width of the traces attached to it. Secondly, resistance of a trace increases with temperature, requiring simulation analyses to determine the final steady state condition. For every 10 degC change in temperature we see a 4% change in resistance of a trace.
These observations point to a need to simulate the PDN design with a DC IR Drop Electro-Thermal solution.
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