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DesignCon 2026
Accelerating AI innovation at the interconnect
Stop by booth #1039 to see how Keysight helps teams accelerate AI innovation by validating next-gen interconnects faster with greater power efficiency. As speeds climb from 800G to 3.2T and chiplet-based 3D architectures add complexity, faster insight is critical to debug early and sign off with confidence. Explore live demonstrations of 3.2T pathfinding, 1.6T interconnect validation, chiplet and 3D IC workflows, PCIe® Gen7 debug, and DDR / LPDDR testing up to 50 GHz.
Book a one-on-one meeting with a Keysight expert to discuss your 2026 goals and toughest validation challenges.
Explore the demos below and plan your booth route.
DATE
February 24 – 26, 2026
LOCATION
Santa Clara Convention Center
Santa Clara, California
KEYSIGHT BOOTH
1039
Eight Live Demos. Pick Your Focus. Get Answers.
See them live February 25–26 at Booth #1039
Designing the Future of AI with Chiplet 3D Interconnect Designer
Accelerate 3D interconnect design for chiplet-based architectures with workflows to model hatched ground planes, optimize 3D interconnects, and simulate SI bridge / interposer behavior early in the design cycle. See it in action with W3510E to reduce risk and speed decisions before tapeout.
Ensuring Signal Integrity at 3.2T Speeds
Get to confident 3.2T signal integrity faster with measurement workflows that shorten time to market. Sweep up to 170 / 250 GHz with a 4-port VNA, generate PAM4 / 6 / 8 eye diagrams, and accelerate iteration with batched AFR enhancements. See it with N5247B, N5292A, NA5307A, 85065A, and N19301B.
Validating Next-Gen Memory for AI Workloads
Bring up new DDR / LPDDR silicon faster with workflows to validate early, probe up to 50 GHz, and optimize signal margin for cleaner compliance and debug. See it in action with D9060LDDC and the LPDDR6 Tx Compliance App.
Reliable PCIe® PAM4 Performance for AI Acceleration
Validate PCIe® Gen7 PAM4 Tx / Rx performance with workflows built for reliable bring-up and faster debug. Maximize DUT margins, pinpoint link issues sooner, and strengthen PCIe® reliability as speeds climb. See it in action with M8199B (x2) and the N1000 + N1046 1 mm kit.
Driving Signal Integrity for AI: 448 Gbps Pathfinding
Push 448 Gbps pathfinding with workflows to generate PAM4 / 6 / 8 signals, analyze 3.2T-class systems, and optimize channel modulation choices faster. See it live with the UXR0902B 80 GHz scope, M8050A BERT, PCIe® transmitter analysis software (SW00PCIE / SW02PCIE), and PCIe® RX test software (N5991P).
Streamlining USB4 Compliance Testing for AI Systems
Speed USB4 compliance for AI systems with workflows that preserve signal integrity while enabling faster, smaller designs. Accelerate compliance testing, catch issues earlier, and move through bring-up with fewer iterations.
Benchmarking 1.6T Interconnects for AI Networks
Validate AI-scale interconnects with workflows to benchmark 1.6T links, measure link quality, and optimize workloads with clear performance data. See it live with INPT-1600GE traffic generation and BERT solutions including M8050A and FITS-8CH.
Validating UALink and Scale-Up Ethernet for AI Infrastructure
Automate compliance and interoperability for AI-scale links with workflows to validate 1.6T speeds, run multi-layer interop tests, and reduce manual effort through automation. See it in action with N1092 / UXR oscilloscopes, compliance software suites (Ethernet 1.6T, PCIe® Gen6 / 7, CEI-112 / 224), and the high-speed test ecosystem including fixtures and probes.
Keysight Education Forum
Ballroom K
Wednesday, February 25, Sessions
Channel Simulation and EOE. One Flow
8:30 to 9:15 a.m.
9:20 to 10:00 a.m.
11:00 to 1:40 a.m.
PCIe®, Increasing Data Rate and the Channel's performance with Optical Links11:50 a.m. to 12:30 p.m..
1:30 to 2:10 p.m.
2:20 to 3:00 p.m.
Conference Papers from Keysight
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