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P5552A PCI Express Protocol Analyzer

Data Sheets



The P5552A PCIe Protocol Analyzer enables deep protocol analysis of PCIe systems in a form factor that is easy to deploy on the lab bench and offers unparalleled signal integrity. The analyzer supports capture and decode for PCIe 1.0 through PCIe 5.0. When paired with the P5551A Protocol Exerciser, incredibly powerful PCIe validation solutions can be built.


Product Overview


The Keysight P5552A PCIe 5.0 Protocol Analyzer features an integrated interposer design which simplifies connection and offers improved signal integrity. By removing the need for a cumbersome external analyzer chassis, setup and versatility on the lab bench are greatly improved. Additionally, this simplified design yields superior signal integrity, ensuring that the analyzer has minimal impact on the channel between the products under test. 


The P5552A supports decode of up to 32 GT/s signaling and lane widths of x4, x8 and x16. Users can utilize up to 16 GB trace depth memory aided by on-board compression which greatly expands the available capture time. The analyzer supports decode of the PHY Layer (TS1/TS2/Ordered sets, Link Layer (ACK,/NAK, sequencing numbers, replay, etc), and Transaction Layer (Memory, Config, and I/O Read and Writes operations, etc)


Trusted Signal Integrity


Debugging complicated interoperability issues between a PCIe Host and Device requires that any protocol analyzer interposer not disrupt the interactions between a Host and Device. The foundation of this in the P5552A is superb control of signal integrity with built in equalization and amplification that effectively removes the effects of the analyzer from the link. This provides the user with confidence that the traffic observed between the Host System and Endpoint are exactly as if the analyzer were not present. 


Other analyzer designs that rely on a separate analyzer chassis often introduce physical and electrical complexities that can impact the channel. In some cases, these interposers inadvertently add channel impairments which can affect the system under test such that it cannot reliably negotiate to the highest mutually supported speeds and lane width. In other cases, an interposer may introduce retiming or redriving capability that can mask issues in the system under test by effectively improving the channel quality and enabling devices to successfully link up in configurations that could not be attainable without the analyzer present. Neither of these conditions is acceptable as they impede the ability of the test and validation engineer to gain a clear and accurate view of what is happening on the link. 


The Keysight P5552A was designed deliberately to avoid these issues, to minimize channel impact and to provide the clearest and most accurate view of the traffic on the PCIe link. Thus, test and validation engineers can focus time and energy on solving protocol issues between the products under test, rather than questioning whether issues have been introduced or masked by their test equipment.


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