HeatWave Technical Papers

Large ΔT at transistor scale is validated by thermography

Source: University of Bristol, U.K.

Figure 1. Temperature line scan through the center of the active region of an AlGaN/GaN HFET (source-drain gap of 4.8 µm, 1.2 µm long gate, 50 µm wide device) on SiC, operated at 1 W, recorded using Raman and IR thermography. For comparison results of a three dimensional finite difference thermal simulation are shown.

Figure 4. Time-evolution of device peak temperature in the center of an AlGaN/GaN ungated device on SiC (15 µm contact separation, 150 µm wide device), operated with 2 µs long square drain pulses (5.3W) at a 50% duty cycle. Simulation results are also shown.

M. Kuball, J. W. Pomeroy, R. Simms, G. J. Riedel, H.F. Ji, A. Sarua, M. J. Uren, T. Martin, “Thermal Properties and Reliability of GaN Microelectronics: Sub-Micron Spatial and Nanosecond Time Resolution Thermography”, 2007 IEEE Compound Semiconductor IC Symposium, October 2007

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Practical Chip-centric Electro-thermal Simulations

Source: ON Semiconductor

• Full-chip dynamic electro-thermal simulation achieved by coupling circuit simulator and thermal solver
• In all cases simulation results agree well with measured data
  

Figure 10. Measured and simulated thermal impulse response. Note the last data-point measured separately at 1000 s.

R. Gillon, P. Joris, H. Oprins, B. Vandevelde, A. Srinivasan, R. Chandra, “Practical chip-centric electro-thermal simulations”, THERMINIC, 24-26 September 2008, Rome, Italy

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Fine Grain Thermal Modeling of 3D Stacked Structures

Source: IMEC, Belgium

• Detailed methodology for thermal analysis of stacked die packages
• Measurements are well matched by a thermal simulation, which computes heat transport through the full-chip layout, including TSVs
  

Figure 6. Schematic representation of the materials in the die stack (not to scale), including the BEOL structure of the top and bottom die.

H. Oprins, M. Cupak, G. Van der Plas, P. Marchal, B. Vandevelde, A. Srinivasan, E. Cheng, “Fine Grain Thermal Modeling of 3D Stacked Structures”, THERMINIC, 7-9 October 2009, Leuven, Belgium

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Electro-thermal modeling/characterization of large lateral PNP drivers

Source: ON Semiconductor

• Temperatures at two discrete points were measured by sensors located in the field of the drivers. Transient Interferometric Mapping (TIM) produced temperature map of the chip at 10µm/pixel spatial resolution by scanning an infrared laser probe beam to the chip backside.
• Segmented according to temperature variations, the power transistor underwent electro-thermal modeling and simulation; the non-uniform current density profile and the thermal profile of the large power driver agree well with measured data.
  

Figure 9. (a) Top view layout of the driver, (b) and (c) show simulated maximal temperature distributions in 2D and along a central axis respectively.

J. Rhayem, A. Vrbicky, R. Blecic, P. Malena, S. Bychikhin, D. Pogany, A. Wieers, A. Baric, M. Tack, "New methodology on electro-thermal characterization and modeling of large power drivers using lateral PNP BJTs", EuroSimE, 26-28 April 2010, Bordeaux, France

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Improve Thermal Profile of Memory-on-Logic 3DICs by Tier-swapping

Source: North Carolina State University

Temperature in the 1024-point, memory-on-logic 3DIC FFT processor for synthetic aperture radar (SAR) was simulated with 80 nm spatial resolution, and was modeled to include the effect of each line of interconnect, as well as each via and fill structure exactly as drawn in the layout. Large isolated temperature spikes were found near groups of clock buffers at the edge of the SRAMs on the middle tier.

By reordering the stackup of memory and logic tiers, it was found that placing the memory tier closer to the heatsink improved not only the thermal profile of the memories but also of the logic tiers. Temperature spikes in the memories no longer significantly impacted the logic tiers, yielding a design where the thermal profile of the tiers were significantly less dependent on each other.

S. Melamed, T. Thorolfsson, A. Srinivasan, E. Cheng, P. Franzon, R. Davis, “Investigation of Tier-swapping to Improve the Thermal Profile of Memory-on-Logic 3DICs”, THERMINIC Workshop, 6-8 October 2010, Barcelona, Spain

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Thermal-aware reliability analysis of nanometer designs

Source: Advanced Micro Devices

• This 3D static thermal analysis flow demonstrates the need to compute temperature at the resolution-level of interconnect metal, via resistors and device fingers, and was used to verify reliability constraints on successive iterations of nanometer-level designs.
• The results obtained using the discussed methodology was compared against alternative approaches to better understand the importance of 3D thermal analysis.

An example full-custom block designed in 45-nm technology is analyzed. The design has close to 800,000 transistors and 150,000 CCRs, and operates on flat, transistor-level extracted data. The total number of power-generating elements, including device and interconnect, is about 4.5 million. Utilizing 30 parallel CPUs, the maximum run time was 8 hours, which included the full 3D thermal simulation.

Figure 4 shows the thermal map of the example block (E). It was simulated in context to the entire core and cache both kept at an uniform power density. They can also be given different power patterns. Power for the E block is spread across the entire GDS, including various metal layers, whereas it is applied on the active region for the rest of the core and cache. The hot spots seen in Figure 4 can be traced back to a single via, metal, or a device.

S. Krishnamoorthy, V. Venkatraman, Y. Apanovich, T. Burd, A. Daga, “Thermal-Aware Reliability Analysis of Nanometer Designs”, 2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 25-27 October, 2010, Austin, Texas

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Robustness Optimization of Power MOSFETs under Inductive Breakdown

Source: ON Semiconductor

The avalanche breakdown of a multi-trenched vertical MOS power transistor is modeled including layout details, and electro-thermally simulated over time.

Figure 1a. Power dissipation in the core device comprising gate trenches, air-gaps and oxide plugs.

Figure 1b. Power dissipation in the termination rings near the semiconductor surface.

Most existing thermal simulation techniques are inadequate, because:

• Breakdown power is dissipated in volumes with significant thickness that are near both the top and the bottom of the vertical transistor. Many thermal simulators model power-dissipating regions in only two dimensions.
• The initial power values during breakdown exceed 7KW. Most thermal simulators cannot converge simulating such high powers, especially at sub-micron length scales.
• Microscale layout features include air-gaps, gate-trenches, and oxide plugs that most thermal simulators cannot model in detail, particularly in a full-chip context.
• These obstacles are overcome, resulting in an accurate electro-thermal simulation of avalanche breakdown. Electro-thermal simulation results agree well with transient temperatures measured with IR thermography, and with measured breakdown-voltage waveforms. Simulation produces the locations and times at which peak temperatures occur, which are very difficult to measure.

Figure 6a. Surface plot of temperature in the termination rings at 25µs.

Figure 6b. Surface plot of temperature in the core device at 80µs.

J. Rhayem, A. Wieers, A. Vrbicky, P. Moens, A. Villamor-Baliarda, J. Roig, P. Vanmeerbeek, A. Irace, M. Riccio, M. Tack, “Novel 3D Electro-Thermal Robustness Optimization Approach of Super Junction Power MOSFETs under Unclamped Inductive Switching”, SEMI-THERM, 20 March 2012, San Jose, California

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