N5991U42A USB4 Version 2.0 Receiver Compliance Test Automation Software
Data Sheets
USB4 Version 2.0 is fully backward compatible with its predecessor USB4, doubles the PHY speed to 40 Gbps per physical lane, and adds the support of asymmetric links. Asymmetric lane arrangement allocates two high-speed differential pairs on each link direction, enabling astonishing 80 Gbps bidirectional transfers. The asymmetric lane arrangement allocates three high-speed differential pairs in one direction, and one differential pair in the other direction, enabling transfers of 120 Gbps and 40 Gbps, respectively.
The backward compatibility implies that each receiver port may have up to 2 lanes that support 10Gbps and 20 Gbps, and optionally 10.3125 Gbps and 20.625 Gbps for Thunderbolt 3 compatibility. The doubled PHY rate of 40 Gbps is achieved by adopting PAM3, a pulse amplitude modulation that defines 3 different signal levels at a given unit interval, running at 25.6 GSymbols/s, and applying advanced symbol encoding techniques. And finally, the asymmetric mode implies that receivers may support up to three lanes.