Column Control DTX

Early Design Review of Boundary Scan in Enhancing Testability and Optimization of Test Strategy

Article Reprints

What is ‘Design For Test’ or ‘DFT’?

It is a concept that influences the design of a component or a system to facilitate in maximizing tests to diagnose maximum defects.

What is ‘Design For Test’ or ‘DFT’?

  • Involves additional test circuitry added to designs
  • Based on Boundary Scan Standard - IEEE 1149.1
  • Test tools and methodologies maximizing defect detection

Where all can this concept of DFT span?

  • Device level all the way to Systems

Device Level DFT

Device being the foundational block of a system, a well thought out DFT architecture always pays off for enabling determinism of quality.

  • Rising number of device vendors provided Boundary Scan enabled chip

Device Level DFT – Defect Detection Between Devices Enabled with IEEE 1149.1

With basic implementation of IEEE 1149.1 enabled devices structural defects on boards arising on digital nodes interfacing with other devices can be detected.

  • Limits the defect detection to IOs on the devices
  • Restricted to type of node interconnects on it

Device level DFT for defect detection inside the device?

  • Basic implementation provides structural defect detection to IO interconnects on the devices
  • What about defect detection inside the chip?

Basic Boundary Scan cells can be leveraged to enable fault detection on nodes inside the chips

Device level DFT for defect detection inside the device – BIST

  • Pattern based and scan based test architectures for internal defect detection.
  • Scan based test logic in the form of BIST (Built-In Self- Test) has made testing more effective and pervasive that can readily be used at any stage of the product life cycle.
  • BIST has made test generation and test application cost-effective. This has enabled in increasing the test coverage to device internals.

Device level DFT for defect detection inside the device – BIST

  • Increase of System-On-Chip and System-In-Package designs necessitates an architecture for a flexible test methodology to be leveraged in multiple phases of the life cycle, ranging from chip test to system
  • Provides flexibility to test at different phases and IPs can be re-used easily into different SOCs.
  • Enabling DFT at a device will help in ensuring that the chips are defect free.
  • New standards - IEEE 1687 and IEEE 1149.1-2013 standard cater to increasing the test logic within the chips.

What are the elements needed to ensure a good Board Level DFT?

  • First step is to choose IEEE 1149.X enabled device for the required functionality, if available.
  • Design teams must qualify JTAG enabled parts to supplement into their functional requirements and specifications.
  • Qualifying new devices compliant to IEEE 1149.1 standard by Procurement team facilitates an effective process for good DFT.
  • Chain the devices with similar logic voltage together

Board Level DFT – Some Basic Good Practices

Devices of similar logic are chained together

Better to keep Power management ICs, out of the chain as it may affect stability of the board during the test.

Board Level DFT – Good Practices

  • On complex designs using a CPLD as a scan path linker, provides better management and flexibility of boundary scan chain in test.
  • A scan path for each circuit (CPU block, Data Processing block, IO management, Memories, etc.) would help control the TAP signals independently.

Board Level DFT – Good Practices

  • Dynamic configuration of system constituting multiple boards enables the boundary scan chain to be tested as a system once all the boards are stacked.
  • Detects any defects resulting from Board-to-Board connector issues

×

Please have a salesperson contact me.

*Indicates required field

Preferred method of communication? *Required Field
Preferred method of communication? Change email?
Preferred method of communication?

By clicking the button, you are providing Keysight with your personal data. See the Keysight Privacy Statement for information on how we use this data.

Thank you.

A sales representative will contact you soon.

Column Control DTX