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Keysight EDA 2025 for High-Speed Digital Design
Keysight EDA 2025 offers new and advanced capabilities for achieving faster design confidence in high-speed digital applications. Keysight EDA’s Advanced Design System (ADS) provides a powerful, integrated design and simulation environment to create digital twins and handle the complexities of today’s SerDes designs, such as chiplets, memory, USB®, and PCIe®. The comprehensive design environment helps you run faster simulations, perform advanced measurements, and gain critical insights to overcome signal integrity and power integrity challenges.
Highlights
Keysight EDA 2025 for High-Speed Digital design includes new and enhanced features and capabilities for the following application areas:
- Chiplet Design
- Memory Design
- PCIe Design
- SerDes Design
- Signal Integrity
- Power Integrity
- EP-Scan
- Design Cloud
Learn more:
Chiplet Design
The Chiplet PHY Designer enables designers to predict the system-level end-to-end link margin with standard-specific measurements such as UCIe’s voltage transfer function (VTF) for the chiplet’s die-to-die interconnects. Built-in support ensures easy setup with key industry chiplet standards.
New features include:
- Crosstalk Analyzer & Design Exploration in Chiplet PHY Designer
- Supported simulation modes – Transient and Bit-by-Bit
- QDR (Quarter-rate clocking) support in Chiplet PHY Designer
- Bus Designer for Chiplet PHY Designer
- Unified simulator for Chiplet PHY Designer
- AMI Model Builder in Chiplet PHY Designer
- Design Exploration and HTML report generation
Memory Design
The Memory Designer minimizes your engineering efforts by utilizing smart design architecture and advanced workflows when setting up various memory interface simulations. It offers the most advanced simulation technologies, including 'forwarded clocking' solutions for jitter tracking and unmatched I/O conditions.
New features include:
- Crosstalk analyzer in Memory Designer
- Supports GDDR7 (Graphics Double Data Rate)
- IBIS pin cloning capability
- Unified Memory Interface Simulator
- Worst-case bit pattern generator using AI/ML
- LPDDR5 compliance solutions
- Lumped matrix model for IBIS sparse matrix model
PCIe Design
The System Designer for PCIe® automates multi-link, multi-lane PCIe system setup with a smart design environment. The PCIe AMI modeler supports both NRZ and PAM4 modulations for quick system implementation. The integrated simulation-driven compliance test solution reduces design iterations and accelerates time-to-market.
New features include:
- Integrated Seasim Interface for enhanced PCIe simulation
- Compliance Probe for comprehensive compliance test coverage
SerDes Design
Keysight EDA’s ADS SerDes design solution offers a comprehensive design and simulation platform that effectively streamlines the SerDes design workflow, empowering designers to overcome challenges, reduce time-to-market, and refine design iterations. It covers various SerDes standards, including PCIe, USB, Ethernet, MIPI, and more.
New features include:
- USB4V2 simulation driven compliance solutions
- PCIe® G5/G6 simulation driven compliance solutions
- Measured waveform AMI model for PAM-n
- Figure of Memit (FoM) calculations in S-Parameter Toolkit
- Custom mask for Smart_Eye_Probe
- HTML report generation for FoM in S-Parameter Toolkit
Signal Integrity
Keysight EDA's SIPro in ADS offers a solution for the analysis of complex high-speed PCBs, enabling you to characterize loss and coupling of high-speed signal nets and extract an accurate EM model that can be used in the ADS system analysis, including Memory and SerDes applications.
Highlight includes:
- SIPro (causality enforced) EM analysis
- Fast DDR analysis
- RapidScan Z0
- Solder Ball/Bump Analysis
Power Integrity
Keysight EDA's ADS with PIPro EM for power integrity provides an integrated engineering environment for end-to-end PI ecosystem simulations. Automation makes it easy to go from PCB EM simulations for DC IR Drop, AC Impedance, and conducted EMI to a digital twin schematic for post-layout optimization and hardware debugging. Highlights include:
- Explore conducted and radiated EMI for a dynamic switching regulator using the CISPR 25 standard setup
- Try out DC IR Drop with a cascade of regulators to investigate multiple power rails in one simulation
- Use AC EM models to optimize decoupling capacitors for high-power multiphase regulator PDNs and then investigate the results with an EMI analysis
This video demonstrates three ways to maximize your PCB design productivity.
Electrical Performance Scan (EP-Scan)
The ultimate Signal Integrity and Power Integrity tool for your hardware design
EP-Scan 2024 Update 1.0 introduces intuitive DC IR drop simulation to EP-Scan. Visualize voltage, current density, and flow on your PDN with the enhanced 2D visualizer. Key updates include support for PAM-2, PAM-3, and PAM-4 in eye diagrams, CSV-driven S-parameter masks, and improved stability and performance.
Design Cloud
Keysight Design Cloud is a new user-experience for cloud and high-performance computing (HPC), enabling you to simulate more and wait less. Highlights include:
- Cloud-based HPC for Memory Designer circuit and EM simulations provide parallel processing for an 80% reduction in simulation times.
- Keysight’s turn-key cloud partner, Rescale, enables you to easily launch unlimited cloud hardware in minutes.
Design Cloud for cloud-based high-performance computing
Keysight EDA Software for HSD Design
Featured Resources
Frequently Asked Questions
Electronic design is the process of creating, testing, and optimizing electronic circuits and systems. It can involve analog, digital, or mixed-signal components and technologies and applies to various domains, such as communications, data centers, and semiconductors.
EDA software is a computer-aided design category of tools for electronic circuits and systems. EDA software tools simulate the behavior and performance of electronic circuits and systems under various conditions and scenarios before fabrication or implementation. They perform different types of simulation, such as logic, functional, timing, electrical, thermal, and electromagnetic, helping designers reduce the risk of design errors, improve the quality of the final product, and save time and money in the development process.
High-speed digital design is a subset of electronic design that deals with the physical layer of digital circuits and communication systems operating at high data rates. It requires special attention to the effects of signal integrity, power integrity, electromagnetic interference, and thermal management. High-speed digital design can enable faster data transfer, lower power consumption, and higher performance in electronic systems.
Standards-driven design is an electronic design method that follows predefined specifications and protocols for communication, data exchange, and interoperability between different devices and systems. Standards-based design can facilitate compatibility, reliability, and scalability in electronic systems. Examples of standards-based design include USB, PCIe®, UCIe, and DDR.
Universal Serial Bus (USB) is a standard for communication and power delivery between devices and hosts, such as computers, smartphones, cameras, and peripherals. USB supports various data rates, from 1.5 Mbps (USB 1.0) to 80 Gbps (USB4 Version 2.0). USB also supports different power delivery modes, from 2.5 W (USB 2.0) to 240 W (USB PD 3.1). USB4 Version 2.0 is the latest version of the standard and is backward compatible with USB 3.2, USB 2.0, and Thunderbolt 3.
Peripheral Component Interconnect Express (PCIe) is a standard for high-speed serial communication between devices and hosts, such as computers, graphics cards, network cards, and storage devices. PCIe supports various data rates, from 2.5 GT/s (PCIe 1.0) to 64 GT/s (PCIe 6.0). The PCI Special Interest Group (PCI-SIG®) defines specifications and compliance tests that guarantee the interoperability of PCIe systems. PCIe also supports different lane configurations, from x1 to x32, to increase bandwidth and performance.
Universal Chiplet Interconnect Express (UCIe) is a standard for high-speed serial communication between chiplets. Designers can combine these small integrated circuits to form larger, more complex chips. UCIe is based on CXL / PCIe and supports the same data rates and lane configurations. UCIe enables chiplet-based designs that reduce cost, power consumption, and design complexity while increasing performance and scalability.
A chiplet is a small, modular chip that performs a specific function very well. For example, a chiplet can be a processor core, a memory block, an I/O driver, or a signal processing unit. Chiplets are designed to be used in a chiplet-based architecture, in which multiple chiplets are connected through a standardized high-speed digital interface, such as UCIe, to form a complete system-on-chip (SoC).
Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) is a standard for high-speed memory communication between devices and hosts, such as computers, memory modules, and graphics cards. DDR supports various data rates, from 200 Mbps (DDR) to 6400 Mbps (DDR5). DDR also supports different memory capacities, from 64 MB (DDR) to 64 GB (DDR5). DDR transfers data on the clock signal's rising and falling edges, doubling the effective bandwidth.
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