Keysight EDA 2024 for High-Speed Digital Design
Keysight EDA 2024 includes the latest release of software for high-speed digital design. PathWave Advanced Design System (ADS) provides a powerful, integrated design and simulation environment to create digital twins and handle the complexities of today’s memory design and SerDes standards. The design environment helps you perform advanced measurements, run faster simulations, and gain critical insights to overcome signal integrity and power integrity challenges.
Custom Mask and Margin Calculation for PAM3 and NRZ
PathWave ADS Memory Designer minimizes your engineering efforts by utilizing smart design architecture and advanced workflows when setting up various memory interface simulations. It offers the most advanced simulation technologies, including 'forwarded clocking' solutions for jitter tracking and unmatched I/O conditions. New features include:
- Shape-driven custom mask margin and margin calculation support for NRZ and PAMn modulations
- Crosstalk limiter for speeding up simulation time while maintaining the simulation accuracy
- S-Parameter simulation within Memory Designer
- Genuine LPDDR5 compliance tests
- BER and Contour for Transient simulator
Memory Design Demo Videos
Discover the most advanced workflow for memory systems using smart components, smart bus wires, and a streamlined workflow embedded in Memory Designer. Including new s-parameter simulation support and cross-talk limiter.
Learn how Keysight supports and helps leading-edge technology development by unlocking pathfinding mode for next generation memory systems. Are you working on pre-DDR6, LPDDR6, GDDR7, HBM4, or beyond? Newly introduced multi-level modulation and a new CA-to-CA ratio require simulator support not found in other EDA tools.
Explore a simulation-driven virtual compliance test workflow for DDR5 and LPDDR5 cases. Performing compliance tests at a much earlier design-stage, reduces risk and increases confidence in the design. The exact same tests that will be run on the first prototype.
Watch how the shape-based mask and mask margin calculations and how a comprehensive report can be generated in Memory Designer. Mask shapes have changed in recent generations of standards, learn how you can assure your design passes the mask spec and generate a comprehensive report.
The PathWave ADS SerDes design solution offers a comprehensive design and simulation platform that effectively streamlines the SerDes design workflow, empowering designers to overcome challenges, reduce time-to-market, and refine design iterations. It covers various SerDes standards, including PCIe, USB, Ethernet, MIPI, and more. New features include:
- Design exploration and HTML report generation with Smart_Eye_Probe
- COM 3.9 and 4.0 support
- Retimer for PAM-n applications support
- IBIS 7.1 for AMI model generation support
Learn how PathWave ADS’s streamlined PCIe workflow helps designers to reduce time-to-market and reduce design spins. The speed of PCIe Gen6 is up to 64Gbps, with the adoption of PAM4 and now employs DFE with weighted sum of DFE tap limits.
SIPro has a net-driven interface, that enables you to achieve layout to results in less than 20 clicks, delivering speed and accuracy.
PathWave ADS with SIPro EM for signal integrity provides a solution for analysis of complex high-speed PCBs, enabling you to characterize loss and coupling of signal nets, and ultimately extract an accurate EM model that can be used in the ADS transient and channel simulators. Highlight includes:
- SIPro (causality enforced) EM analysis
- Fast DDR analysis
- RapidScan Z0
PathWave ADS with PIPro EM for power integrity provides an integrated engineering environment for end-to-end PI ecosystem simulations. Automation makes it easy to go from PCB EM simulations for DC IR Drop, AC Impedance, and conducted EMI to a digital twin schematic for post-layout optimization and hardware debugging. Highlights include:
- Explore conducted and radiated EMI for a dynamic switching regulator using the CISPR 25 standard setup
- Try out DC IR Drop with a cascade of regulators to investigate multiple power rails in one simulation
- Use AC EM models to optimize decoupling capacitors for high-power multiphase regulator PDNs and then investigate the results with an EMI analysis
Power delivery challenges continue to expand. Power Integrity engineers are learning more ways to simulate, optimize, and validate designs before expensive fabrication. This video will show you how to expand the basic Power Integrity workflow with DC, AC, and Transient simulation to include EMI.
Download the ADS workspace for this video:
This video demonstrates three ways to maximize your PCB design productivity.
Electrical Performance Scan (EP-Scan)
The ultimate Signal Integrity tool for your hardware design
EP-Scan simplifies the comparison process between different versions of the printed circuit board design, making it easy to see and report performance differences. Highlights in EP-Scan 2024 inlcude:
- Eye diagram generation
- Net analysis with series components
- Layout view and impedance map
Keysight Design Cloud is a new user-experience for cloud and high-performance computing (HPC), enabling you to simulate more and wait less. Highlights include:
- Cloud-based HPC for Memory Designer circuit and EM simulations provide parallel processing for an 80% reduction in simulation times.
- Keysight’s turn-key cloud partner, Rescale, enables you to easily launch unlimited cloud hardware in minutes.
Design Cloud for cloud-based high-performance computing
Keysight EDA Software for HSD Design
PathWave Advanced Design System
PathWave ADS for signal integrity and power integrity handles the challenges of today’s high-data-rate, densely routed, complex PCB designs. PathWave ADS Memory Designer minimizes the engineering effort required to set up and extract EM models, simulate buses, and perform compliance testing.
Case Studies 2023.09.19
PathWave ADS Memory Designer Turbocharges Design Exploration for Broadcom
Case Studies 2023.09.07
From Overwhelmed to Optimized: SECO's PCB Design Cycle Evolution
Application Notes 2023.08.17
What is the Right Controlled Impedance for Your DDR5 Traces?
Application Notes 2023.06.28
How to Verify Signal Integrity on a Work-in-progress USB4 PCB Design