PathWave High Speed Digital

Keysight EDA 2024 for High-Speed Digital Design

Keysight EDA 2024 includes the latest release of software for high-speed digital design. PathWave Advanced Design System (ADS) provides a powerful, integrated design and simulation environment to create digital twins and handle the complexities of today’s memory design and SerDes standards. The design environment helps you perform advanced measurements, run faster simulations, and gain critical insights to overcome signal integrity and power integrity challenges.


Keysight EDA 2024 for High-Speed Digital design includes new and enhanced features and capabilities for the following application areas:

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Custom Mask and Margin Calculation for PAM3 and NRZ

Custom Mask and Margin Calculation for PAM3 and NRZ.

Memory Design

PathWave ADS Memory Designer minimizes your engineering efforts by utilizing smart design architecture and advanced workflows when setting up various memory interface simulations. It offers the most advanced simulation technologies, including 'forwarded clocking' solutions for jitter tracking and unmatched I/O conditions. New features include:

  • Shape-driven custom mask margin and margin calculation support for NRZ and PAMn modulations
  • Crosstalk limiter for speeding up simulation time while maintaining the simulation accuracy
  • S-Parameter simulation within Memory Designer
  • Genuine LPDDR5 compliance tests
  • BER and Contour for Transient simulator

SerDes Design

The PathWave ADS SerDes design solution offers a comprehensive design and simulation platform that effectively streamlines the SerDes design workflow, empowering designers to overcome challenges, reduce time-to-market, and refine design iterations. It covers various SerDes standards, including PCIe, USB, Ethernet, MIPI, and more. New features include:

  • Design exploration and HTML report generation with Smart_Eye_Probe
  • COM 3.9 and 4.0 support
  • Retimer for PAM-n applications support
  • IBIS 7.1 for AMI model generation support
Design Exploration and Report Generation with Smart Eye Probe

Design Exploration and Report Generation with Smart Eye Probe.

ADS HSD Serdes PCIe Reference Channel

SerDes PCIe Gen 6 reference channel model.

Signal Integrity

Getting simulation models from silicon/chip vendors can be challenging. Jump start your design with standard-specific Transmitter/Receiver models, and reference channel models. Replace the standards-based models with your actual silicon vendor models to improve the quality of your digital twin. New features include: 

  • AMI Modelers for PCIe Gen 5/6, USB4, and Ethernet which uniquely provide a compete reference channel digital twin to obtain a more realistic simulation faster.

Power Integrity

PathWave ADS with PIPro EM for power integrity provides an integrated engineering environment for end-to-end PI ecosystem simulations. Automation makes it easy to go from PCB EM simulations for DC IR Drop, AC Impedance, and conducted EMI to a digital twin schematic for post-layout optimization and hardware debugging. Highlights include:

  • Explore conducted and radiated EMI for a dynamic switching regulator using the CISPR 25 standard setup
  • Try out DC IR Drop with a cascade of regulators to investigate multiple power rails in one simulation
  • Use AC EM models to optimize decoupling capacitors for high-power multiphase regulator PDNs and then investigate the results with an EMI analysis
PathWave ADS High-Speed Digital Power Integrity Conducted EMI

Conducted EMI with PIPro

This video demonstrates three ways to maximize your PCB design productivity.

Electrical Performance Scan (EP-Scan)

The ultimate Signal Integrity tool for your hardware design

EP-Scan simplifies the comparison process between different versions of the printed circuit board design, making it easy to see and report performance differences. By analyzing common fabrication formats like ODB++, EP-Scan shows you the performance of your design as it would be fabricated.

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HSD Apps EP-Scan

Design Cloud

Keysight Design Cloud is a new user-experience for cloud and high-performance computing (HPC), enabling you to simulate more and wait less. Highlights include:

  • Cloud-based HPC for Memory Designer circuit and EM simulations provide parallel processing for an 80% reduction in simulation times.
  • Keysight’s turn-key cloud partner, Rescale, enables you to easily launch unlimited cloud hardware in minutes.
Design Cloud

Design Cloud for cloud-based high-performance computing

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