BERT 64 Gbaud
Master your next design
The Keysight Technologies Inc. M8040A is a highly integrated BERT for physical layer characterization and compliance testing.
With support for pulse amplitude modulation 4-level, 3-level (PAM4, PAM3) and non-return-to-zero (NRZ) signals, and symbol rates up to 64 Gbaud (corresponds to 128 Gbit/s) it can be used for testing devices designed for 400/ 200 GbE, 800G, OIF CEI-56G and CEI-112G, PCIe ® 64/32/16/8/5 GT/s, USB4 Version 2,0, USB 3.2, USB4, Thunderbolt™ 3 and Thunderbolt™ 4.
The M8040A BERT´s true error analysis provides repeatable and accurate results, optimizing the performance margins of your devices.
- Data rates from 2 to 32 and 64 Gbaud
- PAM4, PAM3 and NRZ selectable from user interface
- Built-in 5 tap transmitter FFE with multiple presets to compensate loss
- Integrated and calibrated jitter injection: RJ, LF and HF PJ (multi-tone, sinusoidal), BUJ, clk/2 jitter, sRJ, rSSC, and SSC (spread spectrum clocking)
- Forward Error Correction (FEC) encoding and error insertion for testing DUTs with FEC decoder
- Two pattern generator channels per module to emulate aggressor lane
- Linearity tests with adjustable PAM4 and PAM3 levels
- Interactive link training 2.5/5/8/16/ 32/64 GT/s PCI Express®
- Interactive link training for USB 3.2, 5 Gb/s and 10 Gb/s, x1 and x2
- New SSC clock switch profile supported according to CTS V1.02
- SKP OS filtering for 2.5/ 5/ 8/ 16/ 32 64 GT/s PCI Express® and SKP OS filtering for USB 3.2
- PCIe pre-coder support
- USB4 Version 2.0 pre-coder and scrambler support
- ALIGN filtering for SATA 3G / 6G and SAS 3G / 6G/ 12G
- Short connections to the DUT with remote heads for the pattern generator
- True PAM4 error detection in real-time for low BER levels
- Built-in and adjustable equalization to re-open closed eyes
- Integrated clock recovery and control of external clock recovery units N1076A/B, N1077A, N1078A
- RI and SI level interference injection via M8054A interference source for M8194A/95A/96A AWG
- Graphical user interface and remote control via M8000 system software
- Error distribution analysis to debug burst error conditions, real-time
- Reference clock multiplier support with SSC extended to 64 Gbaud
The M8040A can be used for receiver (input) testing for many emerging interconnect standards, such as:
- IEEE 802.3bs 400 and 200 Gigabit Ethernet (200GAUI, 200GBASE, 400GAUI, 400GBASE)
- IEEE 802.3bj 100 Gigabit Ethernet
- IEEE 802.3cd 50, 100 and 200 Gigabit Ethernet
- IEEE 802.3ck 400 Gigabit Ethernet
- OIF CEI - 56G and -112G (NRZ and PAM4 versions)
- 25G and 50G PON
- PCI Express 64/32/16/8/5/2.5 GT/s
- USB 3.2, USB4 and USB4 Version 2.0
- Thunderbolt 3/4
- DisplayPort 2.1
- MIPI M-PHY Gear 5
- 64G/112G Fiber Channel
- InfiniBand-HDR and NDR
- Proprietary interfaces for chip-to-chip, chip-to-module, backplanes, repeaters, and active optical cables, operating up to 64 Gbaud.
M8000 Series of BER Test solutions
Simplified time-efficient testing is essential when you are developing next-generation computer, consumer, or communication devices
The Keysight M8000 Series is a highly integrated BER test solution for physical layer characterization, validation, and compliance testing.
With support for a wide range of data rates and standards, the M8000 Series provides accurate, reliable results that accelerate your insight into the performance margins of high-speed digital devices.
M8040A High-performance BERT 64 Gbaud
Simplifies accurate receiver characterization of devices operating up to 32 and 64 Gbaud with NRZ, PAM3 and PAM4 signals
Highest level of integration streamlines receiver test setups
With the M8040A, all critical test capabilities for input/receiver (RX) characterization are built in. The pattern generator module provides calibrated and integrated jitter sources and de-emphasis to emulate the transmitter (TX) and to compensate for channel loss in the test setup. In addition, the M8040A provides an internal clock synthesizer and a second pattern generator output channel to emulate an aggressor lane.
The analyzer provides true PAM4 and NRZ error analysis in real time and full sampling to measure down to very low BER and SER.
This high level of integration with the M8040A makes the receiver test set-up connections easier and more robust. Setup and debug time are shortened, calibration is simpler, and the frequency of re-adjustments is reduced, resulting in a more efficient use of overall test time.
Repeatable and Accurate Results with M8040A
The M8040A high-performance BERT provides clean NRZ, PAM3 and PAM4 signals up to 64 Gbaud with fast transitions and low intrinsic jitter. The remote head concept of M8040A with the short 1.85 mm cables brings the performance close to the device under test, minimizing signal degradations caused by lossy channels.
Emulate Stress Conditions for NRZ, PAM3 and PAM4 Input Tolerance Testing with M8040A
M8040A provides all capabilities required for input tolerance test:
- 1 or 2 channels. Second channel can be used as aggressor lane to emulate crosstalk effects
- Data rates are adjustable from 2 Gb/s NRZ up to 64 Gbaud PAM3 or PAM4, selectable NRZ or PAM4 or PAM3
- Algorithmic PRBS, QPRBS, PRTS and memory-based patterns, pattern sequencer with loops, error injection at the bit level (NRZ patterns) and at the symbol level (PAM3 and PAM4 patterns)
- Generates FEC encoded patterns with pre-coder on 1 lane to test DUTs with FEC decoder
- Built-in and calibrated jitter sources that can be used simultaneously: random jitter (RJ), multi-UI low-frequency jitter, multi-tone high-frequency jitter, BUJ, clk/2 jitter, spread-spectrum clocking (SSC), residual SSC (rSSC), spectrally distributed RJ (sRJ)
- Lock system clock to an external reference clock with a multiplying PLL
- De-emphasis for pre- and post-cursor to emulate transmitter de-emphasis and compensate for loss in the test setup
- Inject random interference (RI) and sinusoidal interference (SI) by couplers. The M8000 software controls M8054A, AWG M8195A and M8196A as RI/SI source or as aggressor lanes
- Automated jitter tolerance testing