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W1717 SystemVue Hardware Design Kit

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The W1717 SystemVue Hardware Design Kit (HDK) is a hardware design flow personality that adds onto the core W1461 SystemVue core environment to accelerate the design and verification of digital signal processing (DSP) algorithms in communications and aerospace defense systems. It allows system architects and algorithm developers to create baseband models quickly and validate their performance at the system-level against RF models, test equipment, Standards references, and other signals and conditions.

The W1717 HDK enables a model-based design approach to FPGA rapid prototyping and integrates easily into mainstream design and verification flows. It includes a synthesizable fixed-point model library, and offers a rich set of example designs, ranging from basic filters to realistic communications physical layer design.

Design and verification productivity

System-level modelers and verification engineers can take advantage of SystemVue’s comprehensive integration into hardware design and verification flows. A fixed-point simulation library predicts hardware-like effects without committing to a targeted implementation, and generates synthesizable, hierarchical, RTL-level Verilog and VHDL that is bit-true and cycle accurate. This provides a path to implementation and creates a verification wrapper for polymorphic model-based design flows moving from algorithm to fixed point to RTL and to instantiated hardware. The ability to co-simulate with external hardware description language (HDL) simulators or real hardware is included free with the SystemVue core environment.

Fixed Point Design

Mapping signal-processing algorithms to dedicated hardware with fixed-point arithmetic is often an integral part of the algorithm design and analysis flow. Hardware Design Parts, available in the HDK, can be used to build, simulate and analyze fixed-point systems. A library of over 45 functions, from low-level logic elements to more advanced signal-processing parts such as filters and fast Fourier transforms (FFTs), is available.

The fixed-to-float and float-to-fixed conversion parts provide a means of interfacing fixed-point components with other SystemVue blocks. Hardware Design Parts can also be configured to automatically collect information on dynamic range, overflows and underflows. The parts can be shown in the Fixed-Point Analysis Table to help engineers with system optimization.

The SystemVue HDK supports use of standard-compliant IEEE 1666 SystemC fixed-point data types.

Synthesizable HDL Code Generation

SystemVue’s HDL Code Generation capability provides users an easy path from schematic design to hardware. A user-created SystemVue sub-network model, with only synthesizable fixedpoint parts from the HDK, can be used to generate VHDL/Verilog for the sub-network. For Xilinx’s Virtex-4-7 and Zynq7000 FPGAs, SystemVue provides a path to configure the clock and reset the user’s HDL design, as well as set up Vivado project or generate bit files directly. For Altera’s Cyclone IV/Stratix IV/Stratix V FPGAs, SystemVue provides a similar path to set up a Quartus II project or generate programming files directly.

VHDL/Verilog co-simulation

With the SystemVue HDL co-simulation feature, users can simulate components represented in a HDL, VHDL and Verilog, in the same schematic with other SystemVue components. This integrated capability provides complete design flexibility and complements other SystemVue features, including HDL generation.

HDL co-simulation also allows the user’s existing HDL code to be included in system-level simulations, and integrated with local synthesizable fixed-point primitives. The HDL Code Generator connects the user’s HDL code with other Hardware Design Parts to generate HDL codes for the whole design. It then runs the Xilinx/Altera automatic implementation flow to generate the programming file.

The ability to design all portions of a communications product in one integrated environment eliminates design errors resulting from disconnects among different design teams. By co-simulating with HDL designs, users can easily incorporate existing HDL intellectual property (IP) into new designs, or even co-simulate with SystemVue-generated HDL. SystemVue integrates well with the Mentor ModelSim/Questa or Aldec Riviera-PRO HDL simulators via two simulation modes, either direct simulation from the SystemVue user interface or hierarchical HDL project generation, for full interaction and debugging using the external development environments.

Hardware co-simulation

The SystemVue Hardware-in-Loop (HIL) co-simulation engine allows the dynamic use of FPGA hardware to accelerate computational tasks in a multi-threaded software environment. Effectively, it circumvents traditional bottlenecks where the accelerator hardware would only be usable by a single thread at a time. The engine provides both the hardware implementation and dynamic partial reconfiguration on /7 to implement functions or measurements in FPGA hardware. Programming and run-time simulation connectivity is also supported for the Keysight wideband digitizer families M9703A/B and U5303A. This allows real-time T&M personalities to be prototyped in simulation, then used for custom measurement personalities.

Hardware co-simulation requires a great deal of data stream exchange between processors and FPGA cards. It can be streamed via the PCI Express® bus. In theory, an eight-lane PCI Express Gen 2 bus offers a peak throughput of 500 MB/s. Even though PCI Express suffers from latencies inherent in device drivers and operating system interrupt handling, there are clear advantages to performing hardware co-simulation with a FPGA board using a PCI Express connection to the host processor.

Design Reuse

Design reuse is part of the growing Electronic Design Automation (EDA) industry trend toward repeated use of previously designed components. SystemVue provides two efficient methods for carrying IP into the system-level design environment. The SystemVue environment provides the primary method for design re-use, using sub-network models. SystemVue subnetworks are portable and easily inserted into other design workspaces (e.g., via a copy and paste function). Within SystemVue, they are known as “design” objects, and contain a symbol, schematic, equation, parameters, and notes. Sub-networks can include fixed-point schematics built using the graphical UI, or external HDL code that is instantiated in SystemVue using the HDL co-simulation block.


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