Keysight DDR5 Protocol Solutions

In this comprehensive video, Jennie Grosslight from Keysight Technologies delves into the intricacies of DDR5 protocol solutions using the U4164A logic analyzer system. The presentation begins with an overview of the various interposers available for different form factors, including RDIMM/LRDIMM, DIMM, SODIMM, and ball grid array interposers for embedded DRAM systems. Jennie explains the process of connecting these interposers to the system under test and highlights the importance of mid-bus probing for validation systems.

The U4164A logic analyzer system is showcased for its capability to capture DDR5 command/address traffic up to 8+ GT/s data rates from the smallest signal eyes, ensuring precise acquisition. (DDR5 DQ can also be captured up to 4 GT/s). The video then transitions to the B4661A software, which, when paired with the DDR5 option, provides extensive tools for traffic overview, protocol compliance, and performance analysis. Jennie emphasizes the software’s ability to offer Bus-level signal integrity insights, crucial for setting sample positions and understanding signal behavior.

Addressing the challenges of DDR5, such as ensuring interoperability and identifying root causes of system failures, Jennie outlines how Keysight’s solutions aid in debugging and compliance testing. The video demonstrates the integration of power and signal integrity measurements from external scopes into the logic analyzer waveform, providing a holistic view of system performance.

Jennie also covers the compliance testing features of the tool, including pre-populated JEDEC parameters, detailed summary reports, and the ability to modify test parameters. The post-process compliance tool’s capabilities in violation detection and margin analysis are highlighted, showcasing its utility in identifying potential system failures.

The video concludes with a detailed look at the typical configurations for DDR5 solutions, including the selection of appropriate probes and interposers based on data rates and clock frequencies. Jennie provides insights into the limitations and capabilities of the logic analyzer, ensuring viewers understand the critical aspects of DDR5 testing and validation.