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High-Speed Digital Design Seminar: New features and capabilities in ADS 2023
This High Speed Digital Design Seminar delivers new features and capabilities of Keysight’s PathWave Advanced Design System (ADS) 2023. In this seminar, the following topics were discussed.
- Hear how to accelerate your design process using Memory Designer pre-layout and post-layout workflows.
- Learn how the new Command Address (CA) / Data Bus Pre-Layout Builder is a versatile tool that can reduce your design time for complicated memory buses.
- Discuss new technologies for serializer / deserializer (SerDes) channel and transient simulations. Topics cover the PCIe® AMI Modeler with PCIe Gen5 reference channels, the USB AMI Modeler, and channel simulator support for PAM3, PAM8, and PAM16 signaling.
- Examine the latest addition to the power integrity workflow — a dedicated conducted electromagnetic interference (EMI) analysis method that simplifies a complex task.
- Get an overview of simulation speed-up possibilities with high-performance computing – on-premise or in the cloud.
Download the High-Speed Digital Design Seminar Slides
- Montreal and Ottawa - Memory & SerDes papers (PDF, 11,378 KB)
- Advanced Techniques for Memory Simulation (PDF, 5,046 KB)
- SerDes – PCIe 6 & USB 4.0 (PDF, 4,038 KB)
- Conducted EMI Simulations Made Easy with PathWave ADS (PDF, 4,482 KB)
- Simulate More, Wait Less: High-Performance Computing (HPC) and Cloud (PDF, 1,879 KB)
- Download ADS
- Request a no-charge 30-day evaluation license
- What's New in High-Speed Digital Design and Simulation?
- Four Considerations for HSD Design
- Build AMI Models Faster for DDR5/LPDDR5: PathWave ADS Memory Designer Feature Demo
- Introduction to Simulating with Memory Designer
- Introduction to High Performance Computing in PathWave ADS on Rescale
- High Performance Computing with PathWave ADS Tutorial on Rescale
- Simulating for High-Speed Digital Insights Webinar Series
- Designing Leading Edge Memory Systems