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Get Ready for the Gen5 Wave with PCIe and DDR Technologies
Virtual Seminar
Join us for a virtual seminar with our Keysight PCIe 5.0, DDR5, Simulation experts, and others in your field. We’ll provide presentations, demos, and conversation (Q&A) with industry experts.
This seminar will cover test and validation methodologies, with best practice examples, to help PCIe 5.0 and DDR5 technology adopters fully test all key measurement parameters to ensure their design meets the specification requirements.
Learn the following:
- Evolution of PCIe and DDR technologies
- PHY Layer testing challenges at 32 GHz NRZ and 64 GT/s
- Looking forward to PAM4 technologies
- TX and RX test solutions for PCIe 5.0 and DDR5 Devices
- Simulation and verification environments
- New requirements for DDR5 simulation
TOPICS
- Leading Edge + Mainstream Technologies: Everything is Moving to Next Generation
- Master PCIe Transmitter and Receiver Measurement Techniques
- Latest DDR5 Developments – Planning for DDR6
ORIGINAL BROADCAST DATE
May 6, 2020
DURATION
3 hours
On-demand
Keysight’s Experts
Rick Eads
Principal PCI Express Program Manager
Director, PCI-SIG Member, PCISIG Electrical Work Group (EWG), Card Electromechanical Work group (CEG), Serial Enabling Work Group (SEG)
Co-Chair: GenZ Compliance and Interoperability work group
Perry Keller
Digital Standards and Applications Program Lead
Memory Program Manager
JEDEC Board of Directors
Chairman, JC40.5, JC45.5, and JC64.5 Validation Committees
Stephen Slater
Product Planning and Marketing Manager for SI / PI Simulation Software
Keysight PathWave Software Solutions
Member of SI Journal Editorial Advisory Board
Brig Asay
Strategic Planning Manager
Internet Infrastructure Group
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