Keysight Accelerates Design Data and IP Management for ICs and Chiplets

October 24, 2023

The semiconductor Intellectual Property (IP) market is the fastest growing and largest segment in the Electronic Design Automation (EDA) industry, with demand only predicted to continue. A large part of this is driven by technology innovation, resulting in an explosion in integrated circuit (IC) complexity and semiconductor design data and silicon IP reuse, all of which is prompting chipmakers to collect and manage lifecycle data more effectively. With demand and complexity growing in the market, there is a trend emerging in the ecosystem called chiplet based designs. Chiplets are coming on the market from many different companies and being mixed in a heterogeneous fashion from different process technologies. In fact, Gartner predicted that the semiconductor revenue from systems using chiplets will reach $50.5 billion in 2024.

As demand and complexity in the semiconductor IP market continues to grow, it brings to light the inadequacy of common design data and IP management capabilities. Designers no longer need to create one simple piece of IP. Instead, there is a requirement to pull together multiple IPs to create one system and partition it for a chiplet, while designing this across multiple sites around the globe. The challenge today is no longer just about how to create these big complex ICs, but how design teams from across the world can work together.

To assist designers, Keysight recently expanded its EDA portfolio with the acquisition of Cliosoft, offering customers industry-leading revision control, data and IP management. Unlike other solutions in the market, with this acquisition, Keysight offers comprehensive control and testing, supporting customers throughout the entire lifecycle of design and test data, IPs, SoCs and chiplets. 

An example architecture block based on real world IP. 

One of the challenges is how engineers go about finding these types of IP, either from inside their own company, or externally licensed IP from a third-party vendor. Keysight provides one platform for IP data management, project management and team collaboration. Using this software engineers can create, manage, and share IP by including documents, user experiences, scripts, methodologies, libraries and more. This eliminates the need to manually track down IP usage and everything from creation, design, management and verification is centralized from start to finish, providing clear traceability.  

The other key challenge is how to manage the collaboration between design teams.

Breaking up a system on chip design, by hierarchies. 

If this was a chiplet, it would be managed the same way. The difference is all of these are combined together on one piece of silicon for a System on Chip (SoC), but for a chiplet these could all be individual chips held together on a circuit board with 3D fabrication and packaging, providing a much lower power-based solution. 

Comprehensive verification and test
Alongside improving collaboration with the design team, there is also a diverse set of teams that focus on the test and measurement. Not only is the market growing and therefore there is a natural increase in demand when it comes to testing, but with advances in industries such as automotive, aerospace and defense, there is a growing need to ensure comprehensive testing and verification so any issues can be immediately identified, traced back and resolved. Engineers need to be able to have tools that allow them visibility into the whole product lifecycle, from concept through to production.

While there are traditional products in the market that focus on one aspect, such as the design or testing stage, this is not sufficient. Keysight’s leading EDA portfolio tackles this issue and manages the entire lifecycle, from design to verification and testing.

Webinar
To find out more about how to Master the Art of Managing IP, Chiplets and Design Data sign up for the latest Keysight webinar.

Title: Mastering the Art of Managing IP, Chiplets and Design Data
Date: Wednesday, November 1, 2023
Time: 10am PT