How to Improve SiC Gate Charge Measurements

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Optimize SiC Gate Charge Measurements

Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) gate-charge measurements require capturing gate current and gate-source voltage while controlling the drain voltage, drain current, gate drive, and load conditions. Parasitic inductance in the device and test fixture can introduce oscillation into the gate-current and gate-voltage waveforms, which can distort the resulting gate change (Qg) curve and make the Miller plateau difficult to identify.

Measurement settings can be adjusted to produce smoother waveforms for Qg extraction. Gate resistance can be increased to suppress oscillation, while pulse timing and inductance must be coordinated with the slower switching response. Load selection also affects the resulting curve: inductive and resistive loads produce different waveform behavior, and the appropriate configuration depends on the device and measurement conditions.

Optimized SiC Gate Charge Measurement Solution

Improving SiC gate-charge measurement requires controlling the interaction between gate resistance, switching time, load conditions, and device operating points. The Keysight Power Device Analyzer / Curve Tracer and Advanced Dynamic Power Device Analyzer / Double-Pulse Tester support dynamic gate change (Qg) testing with replaceable Rg designs that allow different gate resistance values to be evaluated while maintaining low stray inductance in the gate loop.. For static measurements, the Power Device Analyzer / Curve Tracer and Advanced Dynamic Power Device Analyzer / Double-Pulse Tester support high-voltage and high-current Qg testing. Selecting suitable gate drive, Vdsoff, and load conditions helps reduce waveform fluctuations and supports more consistent Qg curve generation.

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