The W1462 SystemVue FPGA Architect dramatically cuts design time and verification effort for System Architects and Algorithm Developers doing communications physical layer (PHY) system design. The W1462 bundle adds the W1717 Hardware Design Kit to the W1461 SystemVue core environment, enabling an FPGA hardware design path for rapid prototyping. The W1462 includes fixed-point simulation models, VHDL/Verilog code generation, and hardware in the loop FPGA validation for selected FPGA families. Rapid validation of hardware effects at the system level helps architects produce measurement-hardened algorithms faster than ever before.
The SystemVue core environment also provides a friendly scriptable interface, math and C++ modeling infrastructure, digital filter tool, dataflow and a variety of co-simulation interfaces, and links to test equipment. By adding an FPGA design flow and baseband algorithmic reference libraries, system architects in wireless and aerospace/defense can unite a cross-domain model-based design flow.
Cut physical layer system architecture design effort in half.
Yields designs with higher real-world performance.
Connects with existing design flows through open, standards-based modeling interfaces.
Who will benefit from SystemVue FPGA Architect?
System architects can avoid guesswork and make more optimal design choices and partitioning for high-performance PHYs. HDL generation enables rapid prototyping of working hardware, for faster design maturity and evolution.
HDL hardware designers may incorporate their own HDL IP blocks alongside the blocks supplied by the Hardware Design Kit. This allows for rapid generation of high-quality code, yet allows HDL designers to work at the ESL level in either Gui or text formats, with all the user-interface and verification advantages of the SystemVue platform. SystemVue can be the originating platform for your Comms PHY IP.
Test & Measurement architects can automate high-performance real-time measurements and DSP algorithms (such as digital downconversion, beamsteering, and more).
Open FPGA development environment for the M9703A high-speed digitizer.