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x1149 Boundary Scan Analyzer
Electrical structural test and programming tool based on IEEE 1149.x standards for boundary scan / JTAG technology.
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What's New in x1149 2.0
With the new standard of IEEE 1149.1-2013, you can expect around a 75% increase in test coverage with the following test capabilities:
- Register mnemonic
- IC reset control
- Component initialization mechanism
- Segmented boundary scan register
- Power domain support
- Test mode persistence
- Electronic Chip Identification (ECID)
- Procedural Description Language (PDL)
Highlights
x1149 Boundary Scan Analyzer - Versatile yet Easy to use Board Test Tool
The x1149 is a tool for engineers to perform structural tests, such as open and short tests on their PCBAs. It also performs In-System Programming for devices such as FPGAs and CPLDs.
Additionally, x1149 programs PROM (Programmable Read-Only Memory) devices and execute memory verification tests on devices such as DDR SDRAMs (Double Data Rate Synchronous Dynamic Random-Access Memory).
x1149 2.0 Features
- IEEE Standards
- 1149.1-2013 (New)
- 1149.1-2001
- 1149.6-2003
- 1687-2014
- Custom test with Insert Source Language (ISL) 2.0
- Support Autobank and Scan Path Linker
Test Development
- Maximize test coverage on connectors and non-boundary scan ICs
- Excellent debug tools
- Actionable pin-level failure reporting
- In-system Programming
Applications
- Excellent Test Coverage for Netcom, Server Products, and Automotive customers
- IEEE 1687 Solution for Board Test and Embedded Instrumentation testing
- Automated Configuration of Scan Path Linkers
Key Specifications
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This tool is designed for test development purposes before sending to production for runtime usage. It provides a comprehensive scope of test development features, including configuration, data preparation, test generation, fixture generation, and debugging.
Run time license for Boundary Scan Analyzer provides a comprehensive testing solution that is fully compliant with the latest IEEE 1149.1-2013 standard. This license is designed specifically for production runtime testing.
Provide the capability to test the functionality of embedded instruments within a semiconductor device without defining the instruments or their features.
Provide the capability to test the functionality of embedded instruments within a semiconductor device without defining the instruments or their features.
Result Analyzer is a tool that analyses raw test results to pinpoint the exact device pin location that caused a test failure.
Software Version 2.0 Upgrade Plan for runtime and test development is a service that allows the user to get the latest software revisions for their Keysight x1149 Boundary Scan Analyzer.
Enable the import of external source files to program CPLD/FPGA devices.
Software Version 2.0 Upgrade Plan for runtime is a service that allows the user to get the latest software revisions for their Keysight x1149 Boundary Scan Analyzer.
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