HIGHLIGHTS

  • data rates from 2 to 64 Gbaud PAM4 signal
  • true PAM4 error detection in real-time up to 58 Gbaud
  • built-in de-emphasis, analyzer equalization, and clock recovery
  • integrated and calibrated jitter injection: RJ, PJ1, PJ2, SJ, BUJ, and clk / 2 jitter
  • two pattern generator channels per module to emulate aggressor lane
  • interactive link training and SKP OS filtering for 8 / 16 / 32 GT/s PCI Express®
  • algorithmic PRBS, QPRBS, and memory-based patterns, pattern sequencer
  • for PAM4, gray coding, FEC encoding, and precoder and error distribution analysis
  • all options and modules are upgradeable
  • offers true error analysis and provides repeatable and accurate results, optimizing the performance margins of your devices

Target Applications

The M8040A is designed for research and development engineers and test engineers who characterize chips, devices, transceiver modules and sub-components, boards, and systems with serial I/O ports operating with data rates up to 32 Gbaud and 64 Gbaud in the server, computing, data center, and communications industry.

The M8040A can be used for receiver (input) testing for many popular interconnect standards that use PAM4 and NRZ data formats such as: PCIe 5, TBT3, 400 GbE, 50 / 100 / 200 / 400 / 800 GbE, OIF CEI-56G, and CEI-112G, 64G/112G Fibre Channel, Infiniband-HDR, and proprietary interfaces for chip-to-chip, chip-to-module, backplanes, repeaters, and active optical cables.

The pattern generator of the M8040A Gbaud BERT provides a clean 26.5625 Gbaud PAM4 output signal.

KEY SPECIFICATIONS

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