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PathWave Advanced Design System

High-Speed Digital Design Software

Have confidence in your PCB designs before build-out

Explore High-Speed Circuit Design Courses

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PathWave Advanced Design System (ADS) for signal integrity (SI) and power integrity (PI) is built to handle the challenges of today’s high-data rate, densely-routed, complex printed circuit board (PCB) designs.

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Future-Ready Memory Design

The next generation of double data rate (DDR) memories, such as DDR5 and GDDR6, deliver significant performance. These standards also introduce new SI challenges. Designers must generate IBIS-AMI models for receivers, extract accurate electromagnetic (EM) models of the DDR channel, and predict margin to the eye-mask at specific bit error rates.

PathWave ADS for memory design minimizes the engineering effort required to set up and extract EM models, simulate buses, and perform compliance testing. With the combined capabilities of Memory Designer and SIPro, you can set up your end-to-end DDR analysis five times faster than before.

Watch Webinar
DDR5 Simulation with Memory Designer

Signal Integrity for High-Speed Serial

Each new digital standard brings faster speeds and higher frequencies. Signal integrity engineers need to have confidence in their channel design, including optimal via design, managing crosstalk, signal loss, jitter, and equalization.

With advanced channel simulation in PathWave ADS, you can simulate for pulsed amplitude modulation (PAM-4, PAM-3, and PAM-N) signaling schemes. Complemented by fast and accurate signal integrity EM analysis, you can achieve 100% board success by catching critical errors before build-out.

Attend the Keysight University Course
Designing for Signal Integrity (10 min)

Power Integrity with High Speed Digital Design

Power Integrity: More Than Just DC

With lower voltages, higher currents, and multiple supplies, power integrity issues can be difficult to troubleshoot and cost thousands of dollars to fix. Overcoming this challenge requires a cohesive design flow for frequency and time-domain analysis of power distribution networks (PDNs). With Keysight’s PI design workflow, you can visualize the worst-case ripple caused by a dynamic load and engineer an optimum low-noise PDN.

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W3625B

W3625B PathWave ADS Core, EM Design, Layout, HSD Ckt Sim, SIPro, PIPro

Starting from

Includes post-layout EM verification for high-speed serial signal integrity and power integrity.

W3626B

W3626B PathWave ADS Core, EM Design, Layout, HSD Ckt Sim, Memory, SIPro, PIPro

Starting from

Includes post-layout verification for high-speed serial, memory, Signal Integrity and Power Integrity.

W3627B

W3627B PathWave ADS Core, EM Design, Layout, HSD Ckt Sim, SIPro, PIPro, FEM

Starting from

W3627B includes post-layout verification for high-speed serial, and a highest accuracy EM simulation using the FEM simulator for 3D components like connectors.

W3622B

W3622B PathWave ADS Core, EM Design, HSD Ckt Sim, Memory Designer

Starting from

For next-generation memory design and high-speed serial channel simulation.