Designing Leading-Edge Memory Systems

Table of Contents

• Introduction: Evolving Standards
• A Cohesive Memory Design Workflow
• Next-Generation Memory Interface Design with Equalization
• Solutions to Equalization - Single-Ended AMI Models
• New Innovative Forwarded Clocking solution
• Pre and Post Layout Flow - RapidScan Z₀  and PCB EM Extraction
• Design Exploration and Compliance
• Probing and Performing Measurements
• Measurement and Verification
• Conclusion

Introduction: Evolving Standards

Driven by the high demands of increasing data throughput via video streaming, 5G, artificial intelligence, virtual reality, and the internet of things, next-generation memory technologies have become crucial to keep up. This brings complex design challenges such as increased crosstalk, accurate PCB model extractions, and jitter tracking for optimum DFE settings. The need to simulate, analyze, debug, in a timely and efficient manner is more important than ever.

With next-generation memory including DDR4 and beyond, addressing design challenges including crosstalk, jitter, and JEDEC compliance is key. What signal integrity engineers currently use involves multiple designs and test tools to address these challenges, however, the disconnect from each tool or workflow results in a slow, inefficient workflow.

Keysight’s leading-edge PathWave ADS Memory Designer platform enables you to address these challenges while designing next-generation memory interfaces.

A Cohesive Memory Design Workflow

Designing modern memory interfaces can be a challenging and complex task. The workflow is shown later in Figure 1 highlights a typical memory design workflow, however, there can be additional steps beyond this workflow. It may include additional simulation iterations, setting up and performing measurements, as well as testing the board once manufactured.

The main Memory Designer workflow is targeted for simulation, analysis, and compliance tests. Additionally, there are specific tools that focus on building IBIS/AMI modeling for drivers and receivers. Finally, there are specific electromagnetic simulation features for pre-and post-layout memory channel characterization.

The Memory Designer Workflow begins with the technology selection which can include, but is not exclusive to the following: DDR4, LPDDR4, DDR5, LPDDR5, GDDR6, GDDR6X, GDDR7, HBM2E, HBM3, etc.

Once the technology has been chosen, the memory channel data can be brought in. There are a variety of methods to bring PCB data to analyze, for example, pre-layout or post layout designs using EM extraction tools, or bringing in simulated or measured s-parameter data. This is all within the channel modeling workflow. Once you have the channel data (which could be data bus or command address control buses), the next step is to set up the memory controller and DRAM. If IBIS models are available, you can easily associate them with the controllers and memories. With the IBIS models, you can choose a different model selector, corner cases, ODT (on-die termination) values, and any other model parameters. If you do not have IBIS models, Memory Designer still supports a non-IBIS flow by creating generic IBIS models automatically for you.

The controllers, memory devices, and PCB structures are schematic components, which you can easily wire up your connections utilizing the smart bus wires. The smart bus wires automatically make the connection between components by recognizing the net/node information. The next step is to select the desired measurements such as strobed-eye, eye height, and width, BER (bit-error-rate) contour, or margins by using the smart memory probe component. The available signals and measurements are automatically listed, for easy measurement selection and setup.

A few different simulation technologies support memory interface simulations, including transient convolution, and DDR bus simulation with bit-by-bit and statistical modes.

The Memory Designer workflow ends with data analysis and compliance testing.

PathWave ADS Memory Designer’s cohesive workflow offers a comprehensive memory interface design workflow.

The example shown below in Figure 2 is an example of a complex memory system, consisting of a motherboard with a two-slot SO-DIMM DDR channel. Using the Memory Designer workflow, the whole memory system can be easily constructed and analyzed.