Achieving Better Correlation for PCB Impedance Test
Application Notes
As the operating speed of electronic circuits increases, signal integrity of printed circuit boards (PCB) drastically affects system performance. There is an increasing requirement for controlled impedance PCBs. Impedance tolerance becomes tighter from ± 10 % to ± 5% or even less, and impedance measurements with higher accuracy and better correlation are required as a result. Offset error compensation has been used as a standard compensation method for PCB impedance measurements. However, it has become more difficult to achieve the measurement accuracy and correlation required in PCB manufacturing. The result is lower product yield and measurement discrepancy between PCB suppliers and end users.
This application note describes the difficulties with offset error compensation in PCB impedance measurements and how to overcome them using Keysight’s ENA series network analyzers with TDR.
- Offset error compensation is inadequate for measurement accuracy and correlation to meet impedance tolerance required today due to the inability to remove errors in measurement systems.
- Preparation and compensation operation can be cumbersome when measuring multiple impedance values because offset error compensation is effective when the impedance range is limited.