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Testing PCIe® receiver compliance and interoperability requires a bit error ratio tester (BERT) with a pattern generator that can generate stressed PAM4 signals, as well as a high-bandwidth (>50 GHz) oscilloscope to calibrate the signals and equalizers. The test system needs to operate according to PCIe 6.0's 32 GBaud PAM4 signaling speeds to enable up to 64 GT/s.
Multilevel signaling creates new challenges for reliably testing PCIe 6.0 receivers due to the smaller noise margin. Test automation software simplifies PCIe 6.0 receiver compliance testing, which involves repeatedly applying precisely calibrated, impaired signals to the receiver of the device under test to measure parameters such as the bit error rate under various conditions.
Additional resources for PCIe 6.0 receiver compliance testing
Conformance testing for electrical Ethernet links require bit error rate and forward error correction testing using a bit error ratio tester and high-bandwidth oscilloscopes. Learn how to prove receiver interoperability and conformance to IEEE and OIF specifications at 53 GBd PAM4 signaling using receiver compliance test tools to automate the process.
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Ensuring operation and interoperability of fifth-generation dual data rate (DDR5) devices to JEDEC standards requires the device under test to pass receiver compliance. Learn how to characterize your DDR5 receiver, calibrate your stress signal, and test for DDR5 compliance.
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Verifying Peripheral Component Interconnect Express (PCIe) receiver compliance involves testing the PCIe® 5.0 device's receiver performance with a bit error ratio tester. Learn how to calibrate your stress signal and test for PCIe 5.0 receiver compliance with automated test tools.
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