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Memory Designer in PathWave Advanced Design System (ADS)
PathWave ADS 2019 Update 1.0 includes several exciting new products for high-speed digital (HSD) design and simulation.
PathWave ADS Memory Designer Bundle
For a hardware designer working on memory systems, they must contend with both shrinking timing and voltage margins, and a complex list of compliance measurements to ensure reliable operation. As we move to DDR4 and beyond, random jitter becomes much more significant and the designer needs to have confidence they can pass the Receiver Mask Tests at ultra-low Bit Error Rates (BERs). Keysight’s new PathWave ADS Memory Designer workflow minimizes the engineering effort required to setup, extract EM models, simulate the buses, and perform compliance testing. Offering a unique capability to use the same measurement science for both simulation and hardware verification stages, finally simulation to measurement comparison is made easy.
Predictive. Productive. Insightful.
Figure 1. Memory Designer in PathWave ADS 2019 Update 1.0.
- New schematic components for easy setup of controller, PCB, connectors, terminations and memory
- IBIS files can be applied ‘per device’ giving faster setup and parameterization of settings for groups of signals.
- Automated wiring connections, utilizing Signal IDs found in the layout design
- DDR Bus simulator to characterize signal integrity, capturing margin-to-mask tests for ultra-low BERs
- New Memory Probe to set up measurements by group, with intelligent selection of signal references
- New strobed-eye diagrams and skew measurements
- Automated DDR4 Compliance Test suite and report generation, utilizing Keysight’s industry recognized DDR4 measurement science.
|W2225BP/BT||PathWave ADS Memory Designer Bundle|
|W2393EP/ET||Memory Designer Element|
Learn more about the High Speed Digital Design Flow.