Specifications for PCIe®, USB, DDR, and Ethernet standards frequently change, doubling the data rate with each generation to meet demand for faster speeds.
Lesson 1 - How Emerging Technology Drives New Digital Data Standards
Introduces the trends and challenges of high-speed digital standards, such as PCIe 6.0, USB4, DDR5, and Ethernet. Also covers the benefits of simulation and automated testing for these standards.
Lesson 2 - PCIe 6.0 Technology Overview and Test Challenges
An overview of the PCIe 6.0 technology and its key features, such as PAM4 signaling, forward error correction, and link equalization. Also covers the test challenges and solutions for PCIe 6.0 transmitter and receiver testing.
Lesson 3 - PCIe Technology – Designing for Signal Integrity
A discussion of the signal integrity issues and design considerations for PCIe technology, such as channel loss, crosstalk, jitter, and noise. Also covers the tools and methods for performing signal integrity analysis and optimization for PCIe designs.
Lesson 4 - PCIe Technology - Design Simulation
A demonstration of how to use PathWave ADS to simulate a PCIe 6.0 design and perform channel analysis, equalization optimization, eye diagram analysis, and BER contour analysis.
Lesson 5 - USB Type-C Design Simulation & Automated Testing
Showcases using PathWave ADS for USB Type-C design simulation, including channel and eye diagram analysis, along with compliance testing. Additionally, it demonstrates automating the USB Type-C testing process using PathWave Test Automation.
Lesson 6 - DDR5 Memory Simulation and Analysis
This tutorial showcases using PathWave ADS for DDR5 memory design simulation, including channel, eye diagram, timing, power integrity analysis, and compliance testing. It also demonstrates using an Infiniium UXR oscilloscope for real-world analysis.
Lesson 7 - Ethernet Standards Overview and Testing Challenges
An overview of the Ethernet standards and their evolution from 10 Mbps to 400 Gbps. Also covers the testing challenges and solutions for Ethernet transmitter, receiver, and link testing.
Lesson 8 - Ethernet – Noise and Jitter Measurements
A demonstration of how to use an Infiniium UXR oscilloscope to perform noise and jitter measurements on an Ethernet signal using various tools, such as histogram, jitter separation, clock recovery, eye diagram, mask test, and jitter spectrum.
Lesson 9 - Ethernet - Solving Frame Loss with Forward Error Correction
Illustrates using an Infiniium UXR oscilloscope and an N1092A DCA-M sampling oscilloscope for Ethernet signal Forward Error Correction (FEC) testing. It covers various metrics like Frame Loss Ratio (FLR), Pre-FEC BER (PBER), Post-FEC BER (QBER), FEC Margin (FM), FEC Corrected Errors (CE), FEC Uncorrectable Codewords (UCW), FEC Symbol Errors (SE), FEC Codeword Errors (CWE), FEC Corrected Codewords (CCW), FEC Corrected Symbols (CS), FEC Uncorrectable Symbols (US), FEC Symbol Error Ratio (SER), FEC Codeword Error Ratio (CWER), FEC Corrected Codeword Ratio (CCWR), FEC Corrected Symbol Ratio (CSR), and FEC Uncorrectable Symbol Ratio (USR).
Digital Design and Interconnect Standards
High-speed digital design is challenging, but the right tools can help you overcome the risks.
5th Generation High-Speed Digital Designs Considerations
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High-Performance Digital Products Catalog
From physical-layer characterization to validation and compliance testing solutions, Keysight’s high-performance digital test tools enable you to design, verify, and characterize each step of your design workflow.
PathWave Design and Test Software Catalog
Keysight Technologies introduces PathWave Design and Test Software, a platform that enables faster innovation and insight for electronic design and test. PathWave software boosts productivity by integrating design, simulation, measurement, and analysis tools in a connected workflow.
How to Test and Troubleshoot USB4
USB4 is a high-speed hardware interface that supports multiple protocols through the USB Type-C connector.