Accurate Statistical-Based DDR4 Margin Estimation Using SSN Induced Jitter Model
White Papers
The statistical approach has become popular to design systems where the accurate prediction of random jitter is required at ultra-low BER, and DDR4 is one of the examples. The limitation of this approach is not being able to model the voltage noise due to SSO/SSN, since the statistical approach assumes the system to be time-invariant. This paper proposes a solution that extracts the jitter model from the voltage noise calculated from a transient simulation, then use it for accurate prediction of timing and voltage margin calculation in the statistical analysis. Measurements data is provided to validate the approach.