W1717EP SystemVue Hardware Design Kit

The W1717 Hardware Design Kit is a hardware design personality that adds on to the base W1461BP SystemVue Communications Architect. It provides a fixed-point simulation library and generates synthesizable, hierarchical, RTL-level Verilog and VHDL. When configured with 3rd party synthesis tools, the W1717 provides a path to implementation, and automatically creates a verification wrapper for polymorphic model-based design flow. Finally, the W1717 enables hardware-in-the-loop (HIL) real-time co-verification over a fast PCIe interface, for select FPGA families, and provides a programming interface to the M9703 multi-channel digitizer.

The Verilog and VHDL generated by the W1717 Hardware Design Kit is vendor-neutral between design targets, and provides a great head-start for rapid prototyping and software-defined radio (SDR).

Why should I buy the W1717 Hardware Design Kit?

• Test & Measurement application development: Create wideband measurement algorithms by directly programming the M9703A/B and U5303A digitizer FPGAs. Possibilities include 5G channel sounding, Hybrid Beamforming, MIMO receivers, digital up/downconversion, filtering, and more.
• Rapid-Prototyping: Generate RTL that is transportable between hardware vendors, but still connects to Xilinx Vivado, Altera Quartus II and other synthesis tools.
• High-level of abstraction: Quickly account for bit-true hardware effects prior to targeting, while still at the architecture level, for better BB-RF partitioning.
• Productivity: Integrate your proprietary, hand-optimized HDL blocks or import IP cores from external sources, such as Xilinx CoreGen.
• Real-time Verification: Verify and accelerate algorithms with Hardware-in the-Loop (HIL) co-simulation with Xilinx Virtex 6/7 families over PCIe (such as the ML-605 and VC-707 development boards).
• True Model-based Design: Verify and debug FPGA hardware algorithms in the presence of RF EDA models, Measurement waveforms, and simulation-based wireless Standards references at every level of abstraction. Expand your baseband coverage to RF-BB co-design.

Who will benefit from the W1717 Hardware Design Kit?

• System and SDR architects can avoid guesswork and make more optimal design choices and partitions for high-performance PHYs. HDL generation enables rapid prototyping of working hardware, for faster design maturity and evolution.
• HDL hardware designers can verify hardware designs more easily against RF models, Test Equipment waveforms, and Standards-compliant baseband reference IP.

• Test & Measurement architects responsible for accelerated wideband, multi-channel signal processing, especially for phased arrays and MIMO applications.

What’s Included in the W1717 Hardware Design Kit?

• Fixed-point library containing 45 bit-true, cycle accurate models. Enables fixed-point datatype and simulation mode with block-level/pin-level fixed point histograms and “red-x” overflow/underflow analysis.
• Integration of custom libraries of hand-generated HDL and external IP cores, such as Xilinx CoreGen.
• HDL code generation of RTL-level VHDL/Verilog, complete with design hierarchy, system-level test bench wrappers, test vectors, intelligent creation of clock ready and enable signals.
• Polymorphic model instantiations added for each installed HDL simulator, such as Mentor Questasim, enabling easy model-based scripting and co-simulation, with verification-in-place.
  
• Direct integration of synthesis tools such as Xilinx Vivado and Altera Quartus II from the SystemVue GUI.
• Hardware-in-the-Loop co-simulation. Bring real-time Virtex 6/7 data into SystemVue using development boards such as the ML-605 or VC-707 over PCIe, or test instrument data with the Keysight M9703A/B digitizer.

Figure 1. The W1717 fixed-point library provides over 45 signal processing blocks that are ready for target-neutral HDL code generation. It also provides underflow/overflow diagnostics that assist baseband architects in troubleshooting bit-true finite=precision effects.