DDR and DDR2 – Debugging Intermittent Memory Failures
애플리케이션 노트
Introduction
Why is it that some engineering teams manage to validate and debug intermittent memory failures with relative ease, while other teams struggle through the process? What can you do to make sure you don’t lose valuable time when you are trying to determine the root cause intermittent memory failures?
Typical causes of memory failures include marginal timing relationships, protocol violations, clock integrity issues, signal integrity issues, errors from other buses, incorrect BIOS setting for on-die termination (ODT) and invalid Cas latency.
How do you determine which of these is the cause of the problems in your design?
This application note outlines a debug methodology and introduces tools and techniques that can save you time and give you greater insight into system performance when you are debugging memory failures in DDR and DDR2 systems. (including the SDRAM side of fully buffered DIMM).