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P5552A PCIe 5.0 Protocol Analyzer
The Keysight P5552A PCIe 5.0 Protocol Analyzer introduces a new form factor that is easily deployable in the lab bench environment to enable deep protocol analysis of a PCIe system with unparallel signal integrity. Locate protocol errors or validate device operations by viewing data from the physical layer all through the transactional layer with ease.
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Highlights
See the Real Performance of Your Design
The Keysight P5552A PCIe 5.0 Protocol Analyzer new form factor integrates both the Analyzer and Interposer into one integrated design, simplifying connections and offering improved signal integrity. Say goodbye to bulky chassis setups, interposer card balancing acts, and long heavy cables. With this new design, a smaller lab bench footprint is needed, thus versability is greatly improved.
- Decode up to 32GT/s with support of x4, x8 and x16
- Utilize up to 16GB of trace memory aided by on-board data compression
- PHY Layer (TS1/TS2/Ordered sets), Link Layer (ACK/NAL, Sequencing Numbers, Replay) Transaction Layer (Memory, Config, I/O read/writes)
- Combined analyzer and exerciser software GUI
- Powerful trigger and filter engine
- Stable and solid mechanical connection from the device to the system under test
Key Specifications
P5552A PCIe 5.0 Protocol Analyzer Supports
- 2.5GT/s (Gen1) through 32 GT/s (Gen5)
- CEM connection with x4, x8, and x16 physical lane width support
- 16GB trace memory with data compression
- Packet view, transactional view, and lane view
- Simple and advanced trigger, filter, and quick search
- LTSSM overview with equalization analysis
- Performance overview
- Bifurcation
- DUT configuration space
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