N4891A – 400GBASE FEC-aware Receiver Test

Introduction

Keysight’s N4891A 400GBASE FEC-aware receiver test solution allows measuring frame loss ratio in 400G Ethernet links using FEC by supplying one stressed lane, while maintaining the proper FEC striped test pattern data across all lanes. This solution provides unique insights to understand how component and system design tradeoffs are affected by Forward Error Correction (FEC) requirements and to predict the system margin under real conditions.

400GbE is Revolutionary not Evolutionary

The steadily increasing demand for more computing power and bandwidth fueled by cloud applications has accelerated the deployment of higher speed interfaces in datacenters. The move from NRZ-based 100G interfaces to PAM4-based 400G interfaces is revolutionary, rather than evolutionary: New technologies such as linear broadband amplifiers and drivers as well as adaptive digital equalizers have become a mandatory part of the design but are not sufficient to ensure error-free operation. 400G links typically operate at rather high intrinsic bit error rates (BER) and forward error correction (FEC) is therefore required.

The combination of adaptive equalization and FEC has drastically increased the level of complexity in the characterization and validation of silicon devices, application-specific integrated circuits (ASICs), fiber and copper interconnects, optical transceivers, and the port electronics of switches and routers. Identifying potential performance and interoperability issues at an early stage is critical as answers are complex and time-consuming to solve.

Testing FEC-enabling links

The IEEE 400GBASE standard clauses require the use of the Reed-Solomon code RS (544,514), also known as KP4, to ensure error-free operation. When bit errors are randomly distributed, the system margin and resulting Frame Loss Ratio (FLR) can be easily derived from the pre-FEC BER. However, besides jitter mechanisms and pattern-dependent effects (like inter-symbol interference, ISI), adaptive Decision Feedback Equalizer (DFE) which are necessary to cancel impact of reflection in the links are a major source of error bursts, which can exceed the error correction capability of the FEC, resulting in loss of the entire FEC code word – several thousands of bits of lost data. As such effects have a direct impact on interoperability, 400G Ethernet standards compliance tests for electrical and optical interface require meeting both a conventional BER limit, as well as a Frame Loss Ratio (FLR) measurement.

Overview

Standard compliance tests are performed by stressing one lane at the time, with all other lanes carrying traffic. This is a challenge when coping with the KP4 FEC encoding, which is distributed over all lanes (FEC-striping). N4891A combines the M8040A 64 Gbaud high performance BERT to generate the correct striped FEC test pattern on the single lane under test, along with a N4891A-00x 2- or 4-port 400GE Layer 1 BERT QSFP-DD test system to provide the proper aligned striped FEC traffic on the other 7 lanes enabling it to measure the FLR of the tested interface under stress conditions. This test method is prescribed in the IEEE 802.3 standard clauses 121,122, 124 and 138, 139,140 (802.3bs and 802.3cd respectively).

Features & supported standards

The N4891A solutions generates eight 26.5625 Gbaud PAM4 tributaries according to 50GAUI-1, 100GAUI-2, 200GAUI-4 and 400GAUI-8 recommendations. Interferences can be added on one electrical lane.

Adjustable parameters for the stressed lane

• Data Amplitude (from 100mV to 1.8V pp differential)

• Jitter type (sinusoidal, random, Bounded uncorrelated)

• Periodic jitter frequency (Hz) and amplitude (UI)

• De-emphasis coefficients (2 pre, 2 post)

• Pattern: PRBS, memory pattern and FEC encoded scrambled idle for following interfaces:

o 50GBASE-R (PCS 0&1),

o 100GBASE-R (PCS 0-9 on first channel and PCS 10-19 on 2nd channel)

o 100GBASE-R (PCS 0-19 on the first channel at a 53Gbaud PAM4 coding)

o 200GASE-R (PCS 0&1)

o 400GASE-R (PCS 0&1)

• Additional parameters such as Sinusoidal interferer to Gaussian noise ratio, Eye width/height and can be controlled using the N4917BSCB and M809256PB and M8091BSPA compliance application software

Adjustable parameters for aggressor lanes

• Data Amplitude (from 250mV to 1025mV pp differential)

• De-emphasis (2 pre, 1 post)

• Pattern: 50GE-FEC, 100GE-FEC, 200GE-FEC, 400GE-FEC codewords with scrambled idle,

PRBS31Q, PRBS23Q, PRBS20Q, PRBS15Q, PRBS13Q, PRBS11Q, PRBS9Q and PRBS7Q,

SSPRQ

• Adjustable frequency range of +/- 100 ppm

Measurements

• FEC mode

o Per lane PCS and FEC statistics

o PCS lane marker lock & marker map

o FEC port statistics with count and rate

o FEC symbol bit error distribution analysis statistics

• PRBS mode

o Per lane BER statistics

o Pattern re-lock

• Enhanced BERT mode

o Verbose error stats

o Inferred FEC performance

o Burst error stats

N4891A Requirements

The software components of the N4891A solution run on an external PC or on M9537A embedded controller.

PC hardware requirements

• Operating system: Microsoft Windows 7, Windows 8, Windows 10, (64 bit)

• Memory: 8 GB RAM minimum

• Monitor resolution: WXGA+ (1440 x 900) minimum

PC installed software requirements

• Keysight IO Libraries Suite rev. 17.3x or later

• M8070B system software for M8000 Series, version 6.7.500 or later

• M8070ADVB Advanced Measurement Package for M8000 Series of BERT Test Solutions, version 1.1.550.2 or later

PC interfaces

• USB 2.0 or higher, LAN

• Monitor with Display-Port

Instrument firmware requirements

• M8040A BERT: M8070B system software as above

• N4891A/A400GE-QDD: KiOS version 3.0 or above