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Jivaro for GoldenGate is a parasitic model order reduction tool for use exclusively with Keysight’s GoldenGate RF simulator. Jivaro for GoldenGate creates reduced order netlists for simulation with GoldenGate from existing parasitic extracted views in the Cadence environment. The addition of Jivaro for GoldenGate offers RF IC designers using GoldenGate enhanced simulation speed and capacity with negligible loss in accuracy.
Why should you buy Jivaro for GoldenGate?
- Predictable Extracted Netlist Reduction
- Increase Simulation Capacity and Speed
- GoldenGate Design Flow Integration
Who will benefit?
- RFIC designers who need a robust and predictable solution for simulating large parasitic-dominated post-layout netlists.
- CAD managers trying to optimize hardware resources for a post extracted simulation-capacity requirement that is unsupportable with current hardware.
- VPs of Engineering and design managers who want to reduce the risk of taping out RFICs what have not been properly characterized.
Why it’s better to competing netlist reduction tools
RFIC designers need to simulate circuits with self and mutual inductance in addition to parasitic resistance and capacitance. This creates a simulation-capacity requirement that is either unsupportable with current hardware or requires unreasonable simulation times. Combining GoldenGate with Jivaro for GoldenGate solves this problem.