N9201A Array Structure Parametric Test System

General features

• Option for 4070 Series and 4080 Series of parametric testers
• Multi-channel SMU measurement capability
• One pass platform on 4070/4080 Series
• Concurrent TEG test/measurement

Measurement capabilities

• Up to 40 SMU channels
• 5 picoamp and 100 microvolt measurement resolution
• Address signal generation
• SMU embedded program memory for concurrent measurement

Application for BEOL/Yield ramp Up

• Good for BEOL TEG testing (Resistor,Vth,etc.)
• Concurrent measurement resource for High/Low resolution TEG part
• Improve existing 4070's or 4080's throughput drastically for BEOL TEG testing

Addressable array test structure test capability

• Address Generation Function on Parametric Tester
• SPC (Statistical Process Control) for DFM
• Up to 32 bit parallel address signal generation
• Up to 8 V/125 mA/50 kbps address signal generation

The Keysight N9201A provides a parametric test solution for the yield ramp-up phase by allowing users to test more structures in less time and with greater throughput. With the new Keysight N9201A, Keysight's 4070 and 4080 production parametric testers now offer a per-channel SMU (source/monitor unit) architecture that supports up to 40 total SMUs, five times more SMUs than previously available in a single tester, for extremely fast characterization of in-line array test structures. In addition to a per-channel SMU architecture, the N9201A features an address generation function, allowing engineers to do advanced array matrix testing.

• Our new application note describes how you can improve the parametric test throughput with the Keysight N9201A
• 40 total SMU’s, five times more SMUs than previously available in a single tester, provides extremely fast characterization of in-line array test structures
• Fast, high throughput measurements for yield ramp-up phase, for either back-end of line (BEOL) testing or during in-line test
• Tests larger amounts of test elements, such as resistor arrays and active matrix arrays, than was possible with previous solutions
• Per-channel SMU architecture
• Address generation function for advanced array matrix testing
• Configurations available from 8 to 40 SMUs

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