PathWave RFIC Design (GoldenGate) 2020 includes the following new capabilities:

  • Improvements in Core Performance
  • Links with Electromagnetic Simulations
  • Links with System Simulations


PathWave RFIC DesignPathWave RFIC Design (GoldenGate) 2020 delivers new and enhanced capabilities that improve productivity and efficiency for Silicon RFIC designers.

PathWave RFIC Design

Figure 1. PathWave RFIC Design (GoldenGate) 2020.

Core Performances

  • Support for Cadence IC 618/ICADVM 18
  • Harmonic Balance improvements in speed and memory for large designs
  • Various updates of non-linear models : BSIMBULK 106.2, SimKit
  • Update of TSMC Model Interface (TMI)
  • New Verilog-A compiler

Links with Electromagnetic Simulations

  • Ability to generate data to drive RFPro current excitation
  • Support of reading SIO format for smaller S-Parameters footprint

Links with System Simulations

  • Support SystemVue 2018 Update 1.0 and associated VTBs including new VTBs for 5GNR and IoT
  • New Fast Envelope modeling level for better handling of deep nonlinear memory effects
  • Introduction of Distortion EVM
  • VTBs now embed noise effects
  • Generation of parameterized FCE (will work with upcoming SystemVue 2020)

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