PathWave Design Software Insights

March 31, 2022
Time: 10AM PT / 1PM ET

Join to discuss a new workflow that includes post-layout simulation which integrates both circuit and Electromagnetic (EM) analysis. 

We will cover these key learnings:

• Learn about wide bandgap semiconductors and its role in power electronics
• Understand the new design challenges of wide bandgap semiconductors in SMPS
• Learn a new EM workflow to overcome these challenges
• Understand how a digital reference design can accelerate your time to market
• See Keysight's solution in action: PathWave ADS and PEPro with Reference Designs

April 14, 2022
Time: 10:00 a.m. PT / 1:00 p.m. ET

With memory getting into the multi-gigabit range, the design margins are tighter due to higher crosstalk between vias and traces. Optimizing your design and testing it against specifications is critical. We will discuss the importance of memory channel pre- and post-layout models, how to build them, and how to design with them.

April 26, 2022
Time: 10:00 a.m. PT / 1:00 p.m. ET

The aerospace and defense industry is racing to develop new systems and capabilities. A key to achieving faster, lower-cost development is a Model-based Engineering (MBSE) approach, integrating data through models and predicting performance through ‘digital twin’ architectures. In this session, we will discuss how Keysight’s PathWave System Design software connects to and enables your MBSE flow. It also covers how critical it is to link simulation and measurements to achieve these goals.

April 27, 2022
Time: 10:00 a.m. PT / 1:00 p.m. ET

Until now, doing EMI of simulations required expertise in electromagnetics. In this webinar, we will discuss how to overcome this challenge via post-layout simulation using Keysight's power electronics simulation software.

April 28, 2022
Time: 10:00 a.m. PT / 1:00 p.m. ET

Learn about the latest innovations that you can apply to your Silicon-based device compact model extraction flow.

April 28, 2022
Time: 10:00 a.m. PT / 1:00 p.m. ET

Learn about the latest innovations that you can apply to your Silicon-based device compact model extraction flow.

May 19, 2022
Time: 10:00 a.m. PT / 1:00 p.m. ET

The new PathWave Device Modeling (IC-CAP) release provides a re-designed user interface and usability improvements so you can extract more models in less time. Learn how IC-CAP supports Python 3, integrated plotting, and linkage to customized installations.

May, 25, 2022
Time: 10:00 a.m. PT / 1:00 p.m. ET

Radar coverage is the general term for the space boundary within which a radar meets the mission requirements. They depend on the type of radar and can be described in terms of detection (Pd) and false-alarm (Pfa) probabilities. A Coverage Map is the graphical representation of the radar coverage. In this session, we will discuss a methodology that includes the RF circuit design and signal processing effects in the calculation of the coverage map.

June 21, 2022
Time: 10:00 a.m. PT / 1:00 p.m. ET

Phased Array is an enabling technology for Defense and SatCom applications. The IC market is exploding with new Phased Array IC solutions and choosing the right Digital Beamformer IC (BFIC) is crucial for the complete system performance.

September 20, 2022
Time: 10:00 a.m. PT / 1:00 p.m. ET

With satellite competition growing exponentially, advanced virtual prototyping and design platform techniques are needed to keep pace. Design teams need to drill down into any part of a design, measure components, and bring results back into the system model to simulate with higher fidelity than ever possible.

July 14, 2022
Time: 10:00 a.m. PT / 1:00 p.m. ET

AMI (Algorithmic Modeling Interface) is the industry standard for SerDes transmitter and receiver models. It includes equalization, and CDR (Clock Data Recovery) and helps to simulate the overall channel and to accurately determine BER (Bit Error Rate). In this webinar, we show an easy-to-use workflow to build and use AMI models.

October 13, 2022
Time: 10:00 a.m. PT / 1:00 p.m. ET

Successful memory interface design includes making a robust implementation that works for different corner cases, process variations, BOM changes, etc. However, simulating all these cases can be a daunting task. In this webinar, we will discuss a simple and streamlined workflow for simulating memory interface requirements with PathWave ADS Memory Designer.

November 15, 2022
Time: 10:00 a.m. PT / 1:00 p.m. ET

Due to ever increasing data rates there is less design margin given to memory design engineers. You will have to make sure that your implementation is compliant to specifications. In this webinar, we will walk through the compliance tests and design exploration with several memory standards.