Data Sheets
Keysight’s Vision E400S is the next-generation network visibility solution with comprehensive feature sets to meet the ever-evolving visibility needs of your production network, for up to 400Gbps network speed.
Highly compact and 1RU in size, Vision E400S front panel provides 24 SFP56 and 16 QSFP-DD ports. Each QSFP-DD can break out to many smaller speed ports (200G, 100G, 40G, 50/25/10G) via fan-out cable. It’s the only NPB that supports all possible permutation of speeds, increasing the chance of interoperating with legacy devices while maximizing design flexibility.
The re-programmable nature of the silicon allows fast implementation of a new parser or header stripping option of any new protocols, well-known or proprietary. New load balance options support load balancing per port group. In addition to traditional session-aware load balance, new options also allow asymmetric LB, weighted LB, random LB, and LB using tunneled IP header.
Highlights
• Compact 1RU NPB that supports 10/25/40/50/100/200/400G port speeds
• P4 and Tofino based programmable silicon
• Full-duplex, non-blocking, and line rate L2 forwarding of 9.2 Tbps
• Front panel includes 24 SFP56 and 16 QSFP-DD ports
• Hot-swappable fans, power supplies
• Industry only 400G NPB that supports all QSFP-DD speed permutations: 1x400G, 2x200G, (1,2,4) x100G, (4,8)x50G, (1,2)x40G, 8x25G, 8x10G
• NTP, 1588 PTP and 2 independent 1PPS timing sources
• All ports of all speeds support up to 20 protocols header striping/masking and time stamping (PacketStack+)
• Flexible L2GRE and VxLAN tunneling
• First release supports OOB tool deployments only
• Per port group load balancing. Algorithms include session aware, asymmetric, weighted, tunneled packet type, and random
• Integration with Keysight Visibility Orchestrator (KVO) for Intent Based Visibility (IBV)
• Ease of use, best in the class WebUI
Key Features
• Automated filter compiler resolves overlap rules seamlessly, allowing quickest response to tool or filtering changes without worry of blind spots
• Header stripping, tunnel termination, IP/MAC masking and timestamping on all ports and require no FPGA resources (PacketStack Plus)
• Supports up to 20 protocols header stripping and tunnel termination
• Two banks of load balance options, and load balancing on per port group basis
• Load Balance on both outer IP and tunneled inner IP. All well-known tunnel protocols are supported
• GTP User Plane Load Balance based on inner IP information (User sessions)
• User session filtering inside GTP User Plane tunnels (Explicit tunneled IPv4 and IPv6 filtering)
• Space efficient 1RU design saves rack space in your data center
• Flexible L2GRE and VxLAN tunnel origination. Up to 256 tunnels per chassis.
• Comprehensive wizards make inline tool deployment extremely easy for complex use cases that require tool sharing or VLAN translation
• Secure serial console port with authentication
• Support management port IP allow-list
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