Throughput Comparison Between Medalist i3070 Series 5 and Predecessor i3070 In-Circuit Test Systems

Case Study

The new Keysight Technologies, Inc. Medalist i3070 Series 5 in-circuit test system is designed to enhance throughput.

This case study evaluates the increase in speed of the Series 5 tester compared with its predecessor, the i3070 series. Results showed an overall improvement in test time by almost 30% for the Series 5 compared with the i3070.

Introduction

The Keysight Medalist i3070 Series 5 in-circuit test system is equipped with advanced double density pin cards (12 MPs) and the new analog stimulus and response unit (ASRU) “N” revision card. The ASRU-N includes a new digitized measurement circuit (DMC) and digital signal processing (DSP) algorithm.

These new features speed up the analog testing while maintaining the original measurement operational amplifier (MOA) circuit for users who prefer more accurate measurements. In addition, the advanced double density pin cards will also improve digital test throughput.

Overall, customers will experience about 20% to 30% improvement in test times, which translates into higher production throughput and revenue.

Evaluation objective and board information

The evaluation was conducted for a computer motherboard produced at a high volume production contract electronics manufacturer (CEM) site in Asia. The evaluation objective was to compare the difference between the customer’s existing Medalist i3070 and the new Medalist i3070 Series 5 in terms of:

a) Test throughput

b) First pass yield (FPY) and false reject rate (FRR)

Conversion process

There are two methods to convert the unpowered analog tests. The purpose for both approaches is to add in the “as” option via an off-line computer without affecting the production system time. These two methods are:

I. Manual editing using the graphical user interface

II. Re-running of the interactive program generator (IPG)

In this evaluation, manual editing is chosen to mass edit the unpowered analog test source files.

For speed-up digital tests, change the ‘vector cycle’ and ‘receive delay’ statement to 80 n and 70 n respectively.

Upon completed the editing, first run and debugging are needed to make the analog and digital tests pass consistently with a known good board. All the advanced boundary scan tests and most of the digital tests are passed at the first run without further changes to the vector cycle.

However, some digital tests need to be adjusted to their optimal vector cycles due to the characteristics of the digital components.

Evaluation process

Test throughput

Firstly, ten known good boards are chosen to run on the Medalist i3070. Test time is collected after tests are matured (after at least three cycles of execution). The same steps are repeated for the Medalist i3070 Series 5. 

The test throughput improvement enabled by the Series 5 ICT system is evident, with board cycle time reduction by over six seconds, which is about 28% improvement. Do note that the tests have been optimized using the auto optimizer feature which is available in earlier software versions. 

First pass yield and false fail rate

A total of 428 boards are used to benchmark the first pass yield (FPY) and false reject rate (FRR). Two true failure boards are intentionally added into the sample size. These boards are first tested on Medalist i3070, and the same sample boards are used on Medalist i3070 Series 5.