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The Genesys PLL Synthesis module gives RF designers the ability to quickly analyze analog PLLs and synthesize their loop filters for a variety of RF board applications, without requiring an array of general-purpose simulators or libraries that are not well-suited to the task.

Genesys PLL Synthesis augments general-purpose circuit and system-design flows for the task of analog PLL design. It is a self-contained application with its own simulators and algorithms that have been optimized for the task of analyzing loop performance, as well as synthesizing the loop filters needed to realize the PLL. Unlike Spice, harmonic balance, linear simulators, spreadsheets and other general-purpose tools, PLL Synthesis is fast and optimized for the task of analog PLL design.

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PLL Synthesis accounts for:

 

  • Reference source characteristics, including phase noise breakpoints, loaded Q, impedance, power level
  • 4 different types of phase detectors, and their characteristics (Phase/freq detector, Charge Pump, Mixer, XOR)
  • A wide variety of Integrators and extra loop filters, their characteristics
  • VCO characteristics, including user-defined tuning table and phase noise
  • Non-idealities and noise in op-amps that may be used in the block diagram

PLL Synthesis performs the following analysis functions:

 

  • Frequency response
  • Transient response, to see settling and stability
  • Phase noise performance
  • Response plots with markers and scrolling windows for long traces
  • A graphical view of your PLL block diagram, with a detailed text summary

PLL Synthesis performs the following synthesis functions

 

  • Loop filter synthesis for a variety of topologies and loop orders
  • 5 setup wizards that lead you through the design process for
    - Frequency Synthesizers
    - Phase Modulators
    - Frequency Modulators
    - Phase Demodulators
    - Frequency Demodulators

This powerful synthesis capability is available in the following Genesys bundles:

Return to the Genesys Product Structure & Options Summary.