Engineering at the Edge Webinar Series - Episode 2

About this event

Engineering teams are facing a fundamental shift. As data rates climb, frequency ranges expand, and AI systems scale, traditional validation approaches are being pushed to their limits, and many teams are already running into these challenges.

This four-part series explores what changed, where validation breaks down, and how engineers are adapting. You’ll see how teams validate 800G interconnects, multi-terabit optical links, and large-scale AI clusters across the full lifecycle, from pre-silicon design to lab measurement, network emulation, and manufacturing test.

Each session focuses on practical changes in tools, workflows, and measurement strategies that help identify issues earlier, reduce costly rework, and ensure systems perform reliably at scale.

Join the series to understand what’s changing, where systems reach their limits, and how to build a validation strategy that keeps pace with next-generation technologies.

Episode 1 - How Data Rates Doubled, and Where Validation Reaches Its Limit 

Data rates have doubled, but validation methods have not kept pace. As PCIe, DDR, and multi-terabit optical interconnects evolve, engineers are encountering signal integrity challenges much earlier in the design process.

Episode 2 - How Frequency Ranges Expanded, and Why Measurement Fidelity Became Critical

As systems move into higher frequencies and wider bandwidths, small measurement errors can lead to costly design decisions. Engineers working in wireless, radar, satellite, and optical domains must now validate signals that push existing tools to their limits.

Episode 3 - How System Scale Expanded, and Why Network Traffic Validation Became Essential

AI data center networks now operate at a scale where device-level validation no longer reflects real performance. Engineers must understand how systems behave under realistic traffic conditions, not just in isolated tests.

Episode 4 – How Manufacturing Complexity Increased, and Why Validation Had to Evolve

As semiconductor complexity increases and board designs become denser, manufacturing teams face tighter tolerances, reduced test access, and rising pressure to maintain yield and throughput. Validating RF performance and high-speed digital signal integrity at production scale adds a new layer of complexity that traditional approaches struggle to address.