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White Papers
High-speed digital standards are evolving to keep pace with emerging technologies such as 5G, the Internet of Things (IoT), artificial intelligence, and autonomous vehicles. While each technological advancement raises the bar for innovation, each step forward brings new obstacles, particularly for hardware engineers designing memory systems.
High-speed memory designers are currently facing a wave of new challenges. The need for faster double data rate (DDR) memory architectures drives a significant need for more bandwidth and low latencies in data centers. According to market analyses, DDR chip sales account for more than a third of total semiconductor revenues, and electronic systems use at least 50 percent of that number. The prediction for DDR use will continue to increase to an estimated 80 percent over the next few years.
The industry is transitioning from the current DDR4 memory to DDR5 with its promise of 4,800 megatransfers per second (MT/s) per pin. A practical, simulation-based design and analysis workflow is critical to support this technology successfully.
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