New LDMOS Model Delivers Powerful Transistor Library— Part 2

The conclusion of this 2-part article shows that the CMC model can be scaled for a larger device, with a good fit for signal, power and distortion performance—illustrated by a 60 watt Doherty power amplifier design example

 Last month, Part 1 of this article introduced the new CMC (Curtice/Modelithics/ Cree) non-linear LDMOS FET transistor model. The CMC model was described, and its utility demonstrated by making extractions on a 1 watt wafer-probeable FET. In Part 2, this device is used as the core of a 30 watt model to show the scalability to larger devices. The 30 watt model is built up by adding appropriate package parasitics and thermal model parameters to a scaled version of the 1 watt cell model and then validated against linear and non-linear measurement data. A 19 element high power transistor library based on the CMC model is also explained. This library covers devices of various power levels up to 90 watts and frequencies over the DC to 2.7 GHz range. As an example of the good results that can be achieved with the new model library, a 60 watt UMTS band Doherty amplifier, employing the CMC UGF21030 LDMOS FET model, has been designed, achieving excellent efficiency and linearity simultaneously, with simulation- to-measurement agreement far exceeding that achieved with models available previous to the CMC. 

Modeling of a 30 Watt Packaged LDMOS FET Transistor 

The die used in the 30 watt Cree UGF21030 transistor has the same cell layout as employed in the 1 watt FET. A major feature of the CMC model is that it has been found to scale very well with increasing gate width through the use of the AREA parameter. In developing the UGF21030 model, this feature was used to scale the 1 watt core device model to 30 watts. Next, the thermal resistance was changed, using the R_TH parameter, to include the heat-sinking effects of the package and finally, the package model was developed. The package modeling approach adopted was to measure and calculate the parasitic capacitances of the package and to calculate the wire-bond inductances of the internal matching structures. The bond wire inductances were calculated to include any mutual coupling effects. Figure 1 shows the partitioning of the parasitic elements in comparison with the physical positioning of the die. With the complete package model in place, the element values were then refined by comparing simulated data with measured S-parameter and load pull data. Resistive losses were also added at this point. The transmis- sion line elements, as seen in Figure 2, were included to compensate for measurement reference plane issues associated with the drain wire bond manifold and the package bond shelf. 

 Conclusions 

A powerful new large signal LDMOS FET model has been developed and, shown to scale well in translating from die to larger packaged devices. The model has enabled a very versatile library of high power transistor models addressing powers to 90 watts and frequencies to 2.7 GHz. Library model accuracy has been demonstrated in a complex application that requires all regions of DC and RF operation to be well modeled. The results of this work show excellent agreement between simulations and measurements of the complete Doherty amplifier. Of considerable importance is the fact that the transistor model is capable of providing wide band simulations. The model has also provided further insight into the operation of higher power Doherty amplifiers and has highlighted some of the sensitivities of these designs. The number of variables in the Doherty amplifier makes practical tuning methods ineffective. Having an accurate large signal model allows the power amplifier designer to engineer more complex architectures with confidence.