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FPGA-based averaging can improve measurement results
Any individual measurement is likely to contain some amount of noise that may obscure the signal of interest or, for example, its harmonic content, modulation sidebands, and so on. Averaging is a form of signal processing that can reduce noise effects, improve the signal-to-noise ratio (SNR), and reveal more details about the signal of interest. It can also produce improved resolution and dynamic range.
Many of Keysight’s high-speed digitizers feature onboard field-programmable gate arrays (FPGAs) that are designed to address real-time applications that require fast sample rates and wide bandwidth. The firmware included in the FPGA board allows real-time data processing capabilities such as peak detection and signal averaging. For signal averaging, three advanced techniques are also supported: noise-suppressed accumulation, segment accumulation and “ping-pong" accumulation.
In applications such as time-of-flight spectroscopy, the signal is a rare event that rides on top of a noisy baseline. FPGA processing reduces the random noise and ultimately enhances the digitizer’s ability to detect such signals in the presence of noise. The averaging firmware within the FPGA board allows the user to set a threshold that must be exceeded before a data value is entered into the sum.
To simplify overall system design and avoid overflows in the summed data, the noise base can be subtracted from each data value before the summation is performed. The FPGA firmware implements a similar capability for negative-going signals.
In many time-resolved applications, multiple averaged waveforms must be acquired with very low dead time between measurements. This can be accomplished by segmenting the averaging memory. In Keysight digitizers, the segment length is user programmable and from 1 to 128,000 separate accumulations of summed data can be stored. The dead time depends on the size of the segment.
To increase measurement rates, the FPGA-based averaging process allows ping-pong accumulation and processing. After the dead time and at the end of each segment accumulation within the FPGA, a new accumulation can begin before any readout of the previous accumulation. Even as the accumulation continues, the previous segment can be read out through a high-speed bus.
Learn more about FPGA Design / Development Solution